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PRELIMINARY DATA SHEET
MICRONAS
DPL 3520A, DPL 3519A, DPL 3518A Dolby Pro Logic Processor Family
Edition July 31, 1997 6251-423-1PD
MICRONAS
DPL 35xxA
Contents Page 4 6 6 6 7 7 8 8 9 12 15 17 17 18 21 26 27 28 28 28 28 28 28 28 29 29 29 29 30 31 32 33 33 35 35 36 37 37 38 39 39 40 40 2 Section 1. 2. 2.1. 2.2. 2.3. 2.4. 3. 3.1. 3.2. 3.3. 3.4. 3.5. 3.5.1. 3.5.2. 3.5.3. 3.5.4. 4. 4.1. 4.2. 4.2.1. 4.2.2. 4.2.3. 4.2.4. 4.3. 5. 5.1. 5.2. 6. 6.1. 7. 8. 9. 9.1. 9.1.1. 9.1.2. 9.1.3. 9.1.4. 9.1.5. 9.1.6. 9.1.7. 9.1.8. 9.1.9. 9.1.10. Title Introduction Functional Description Features of the Analog Input Section Features of the DSP-Section Features of the Analog Output Section SCART Switches
PRELIMINARY DATA SHEET
Specifications Outline Dimensions Pin Connections and Short Descriptions Pin Configurations Pin Circuits Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions Characteristics Measurements according to Dolby specifications, typical values I2C-Bus Interface Protocol Description Proposal for DPL I2C-Telegrams Symbols Write Telegrams Read Telegrams Examples Start-Up Sequence Audio PLL and Crystal Specifications Operation with Crystal Operation without Crystal I2S-Bus Interface I2S Bus Timing Diagram Power-up Sequence Programming the Mode Register Programming the DSP Part Summary of the DSP Control Registers Volume Channel 1 and Channel 2 Balance Channel 1 and Channel 2 Bass Channel 1 and Channel 2 Treble Channel 1 and Channel 2 Loudness Channel 1 and Channel 2 Spatial Effects Channel 1 Volume SCART Channel Channel Source Modes Channel Matrix Modes SCART Prescale Micronas
PRELIMINARY DATA SHEET
DPL 35xxA
Contents, continued Page 40 41 41 41 42 42 43 43 43 44 44 44 44 44 44 45 45 45 46 46 47 47 47 47 48 48 48 49 50 51 52 53 53 54 56 56 Section 9.1.11. 9.1.12. 9.1.13. 9.1.14. 9.1.15. 9.1.16. 9.1.17. 9.1.18. 9.1.19. 9.1.20. 9.1.21. 9.1.22. 9.1.23. 9.1.24. 9.1.25. 9.2. 9.2.1. 9.2.2. 10. 10.1. 10.2. 10.2.1. 10.2.2. 10.2.3. 10.3. 10.4. 10.5. 10.6. 10.7. 11. 12. 13. 13.1. 13.2. 14. 15. Title I2S1 and I2S2 Prescale ACB Register, Definition of the SCART-Switches and DIG_CTR_OUT Pins Beeper Mode Tone Control Equalizer Channel 1 Surround Decoder Modes Surround Reproduction Modes Surround Source Modes Surround Source Matrix Modes Surround Delay Surround Manual Input Balance Surround Input Balance Mode Surround Spatial Effect Panorama Sound Effect Surround Reverberation Summary of Readable Registers Quasi Peak Detector Digital Input Level Register Further Explanations and Application Hints Overview of the Surround Decoder and Reproduction Modes Useful Combinations of the Surround Decoder and Reproduction Modes Useful Combinations with the ADAPTIVE Surround Decoder Mode Useful Combinations with the PASSIVE Surround Decoder Mode Useful Combinations with the EFFECT Surround Decoder Mode Further Notes Input and Output Levels for Dolby Pro Logic Operation Dolby Qualification Phase Relationship of Outputs Minimum Control Transmissions for DPL 3520A Application Principle of the DPL 3520A Application Circuit Diagram of the DPL 3520A Dolby Pro Logic Processor Family DPL 3518A: Basic Dolby Pro Logic Coprocessor for the MSP Family DPL 3519A: Advanced Dolby Pro Logic Coprocessor for the MSP Family IC Failure Report Data Sheet History
DPL 3520A Dolby*) Pro Logic Processor Note: This document contains information on a new product. Specifications and information herein are subject to change without notice. *) "Dolby", the double-D symbol and "Pro Logic" are trademarks of Dolby Laboratories Licensing Corporation. Micronas 3
DPL 35xxA
Dolby Pro Logic Processor Family 1. Introduction The DPL 35xxA processor family is designed to decode Dolby encoded surround sound. The ICs integrate the complete Dolby Surround Pro Logic decoding on chip without any necessary external circuitry. This data sheet describes the features and specifications of all members of the IC family. The DPL 3518A is designed as a coprocessor to one of the TV sound processing ICs of the MSP 34xx family. It only has digital interfaces. No analog input and output interfaces are supported. The DPL 3519A is also designed as a coprocessor to the MSP family but has analog output channels in addition to the features of the DPL 3518A. Together with the MSP, a TV set with up to six outputs (L, R, C, SUB, SL, SR) can be developed together with headphones and several line outputs. The DPL 3520A is designed as a stand-alone Dolby Surround Pro Logic decoder. An on-chip A/D converter digitizes analog inputs. The DPL 3520A can also be used as a coprocessor to the MSP 34xx single-chip Multistandard Sound Processor family. This gives another A/D input pair to the system. The ICs of the DPL family are pin-compatible to the MSP ICs. This speeds up PCB development for customers using MSPs. The software interface is largely the same as for the MSP 3400C. Volume, tone controls, matrixes and switches use the same registers and values. Thus, the standard MSP 3400C controlling software can be used to control the DPL 3520A. Little overhead is needed to control the Dolby Pro Logic part of the IC.
PRELIMINARY DATA SHEET
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PRELIMINARY DATA SHEET
DPL 35xxA
DPL 3518A Integrated Functions: - - - - - - - - - - - - - - - - - Full Dolby Surround Pro Logic Adaptive Matrix Pseudo-surround mode for signals not encoded in Dolby Surround PANORAMA sound mode (3-D Surround sound via 2 loudspeakers) Noise sequencer Automatic input balance control 7 kHz low-pass filter 100 Hz low-pass filter for subwoofer Modified Dolby B-type NR decoder 30 ms surround delay according to table created by Dolby Laboratories (1 ms steps) 2 I2S input channels (e.g. MSP and DRPA) 2 I2S output channels, freely programmable with sound channels L/R (resp. L)C/R)C), C/S, Sub or I2S input Mode control: normal/phantom/wide/three channel/center off/panorama sound/stereo bypass Surround matrix mode control: adaptive/passive/effect Additional surround basewidth effect Reverberation of surround signals 2 digital input/output pins 1 digital input pin
DPL 3519A Integrated Functions (in Addition to all DPL 3518A Functions): - - - - - - - - Master volume control in dB units Level Trim for L, C, R, S in dB units, $12 dB Identical treble/bass/loudness function for L, C, R, S 5-band equalizer for C channel Separate volume control for two surround outputs Additional line output for HIFI receiver connection (SCART output). Volume for this output is in dB units. 3 pairs of D/A converters Scart switches
DPL 3520A Integrated Functions (in Addition to all DPL 3518A and DPL 3519A Functions) - 1 pair of A/D converters - Note: the 5-band equalizer for C channel can only be used in coprocessor mode. No parallel AD input possible.
DPL 3520/19/18A Applications: Dolby Pro Logic Surround System in television sets in satellite receivers in video recorders
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2. Functional Description In the following, the functional description of the DPL 3520A is given. See section 13 for the modified block diagrams of the DPL 3518A and DPL 3519A. Block diagram: DPL 3520A consists of three blocks: - analog input section containing channel selection and 2 high-quality A/D converters - DSP section performing audio baseband processing - analog output section containing 6 D/A converters with 4-fold oversampling Control-bus: - The IC is controlled by The device addresses are 80hex/81hex, 84hex/85hex and 88hex/89hex. Clock System: - Single crystal clock system (18.432 MHz), alternatively external clock. Packages: - 68-pin PLCC package - 64-pin Shrink DIP package - 52-pin Shrink DIP package I2C-bus. I2C-bus Power Consumption: - typical: 450 mW at 5V - typical: 120 mW at 8V
PRELIMINARY DATA SHEET
2.1. Features of the Analog Input Section - three selectable analog pairs of audio baseband inputs (+ three SCART inputs) Input level: v2V RMS; input impedance: w25 k - one selectable analog mono input; Input level: v2V RMS; input impedance: w10 k - 20 Hz to 20 kHz Bandwidth for SCART-to-SCARTcopy facilities - two high-quality A/D converters 2.2. Features of the DSP-Section - flexible selection of audio sources to be processed - 4-channel digital input via I2S-Bus and 4-channel digital output via I2S-Bus. - digital baseband processing: volume, bass, treble, loudness on output channels 1 and 2. - Dolby Pro Logic processing - 100 Hz low-pass for subwoofer - 30 ms delay line A block diagram of the DSP software is shown in Fig. 2-2.
I2S_DA_OUT1 I2S_DA_OUT2 I2S_CL I2S_WS I2S_DA_IN1 I2S_DA_IN2
I2S Interface
I2S1/2L/R I2S1/2L/R OUT1_L
D/A D/A
OUT1_L OUT1_R
Mono
MONO_IN
OUT1_R
Channel 1 Output
DSP
SC1_IN_L OUT2_L OUT2_R
D/A D/A
OUT2_L OUT2_R
SCART1
SC1_IN_R
Channel 2 Output
SC2_IN_L
A/D A/D
SCART_L SCART_R
SCART_L SCART_R
D/A D/A
SC1_OUT_L
SCART2
SC2_IN_R
SCART 1
SC1_OUT_R
SC3_IN_L
SC2_OUT_L
SCART3
SC3_IN_R
SCART Switching Facilities
SCART 2
SC2_OUT_R
Fig. 2-1: Block diagram of the DPL 3520A 6 Micronas
PRELIMINARY DATA SHEET
DPL 35xxA
Channel1 Matrix SCARTL SCARTR Prescale
Equalizer or Bass/Treble Loudness Spatial Effects Bass,Treble Loudness Spatial Effects Beeper
Volume
OUT1L OUT1R
Balance
Channel 1 Output
Analog Inputs
Channel2 Matrix
Bass,Treble Loudness
Volume Balance
OUT2L OUT2R
Channel 2 Output
I2S1L I2S1R I2S2L I2S2R
Prescale Channel Source Select SCART Channel Matrix Volume SCARTL SCARTR
I2S Bus Inputs
SCART Output
Prescale
I2S1 Channel Matrix
I2S1L I2S1R
I2S1 Output
L/L+C/PSL Surround Source Select R/R)C/PSR Surround Source Matrix Dolby Pro Logic or Passive or Effect
I2S2 Channel Matrix
I2S2L I2S2R
I2S2 Output
C S C SUB Quasi-Peak Channel Matrix Quasi peak readout L Quasi-Peak Detector Quasi peak readout R
Noise Generator
I2S1L
Internal signal lines
Fig. 2-2: Firmware block diagram
2.3. Features of the Analog Output Section - channel 1 and 2: two pairs of 4-fold oversampled D/Aconverters Output level per channel: max. 1.4 VRMS Output resistance: max. 5 k S/N-Ratio: w85 dB at maximum volume; max. noise voltage in mute mode: v3 V (BW: 20 Hz...16 kHz) - one pair of four-fold oversampled D/A-converters supplying two selectable pairs of SCART-Outputs. Output level per channel: max. 2 VRMS Output resistance: max. 0.5 k S/N-Ratio: w85 dB (20 Hz ... 16 kHz) 2.4. SCART Switches
SCART_IN SC1_IN_L/R MONO SC2_IN_L/R SC3_IN_L/R 2 2 2 2
ACB[1:0] 00 01 10 11 S1 A D 2 SCARTL/R to Audio Baseband Processing (DFP)
ACB[3:2] 2 2 from Audio Baseband Processing (DFP) SCARTL/R D 2 A 2 11 S2 2 00 01 2 10 SC1_OUT_L/R
SCART_OUT
ACB[5:4] 2 00 01 10 S3 2
The analog input and output sections offer a wide range of switching facilities, which are shown in Fig. 2-3. The switches are controlled by the ACB bits defined in the audio processing interface (see section 9. Programming the DSP Part). If the DPL is switched off by first pulling STANDBYQ low, and then disconnecting the 5 V, but keeping the 8 V power supply (`Standby'-mode), the switches S1, S2, and S3 maintain their position and function. This facilitates the copying from selected SCART-inputs to SCART-outputs in the TV-sets standby mode. Micronas
2 2
SC2_OUT_L/R
Fig. 2-3: SCART-Switching Facilities Bold lines determine the default configuration
In case of power-on start or starting from standby, the IC switches automatically to the default configuration, shown in Fig. 2-3. This takes place after the first I2C transmission into the DFP part. By transmitting the ACB register first, the default setting mode can be changed. 7
DPL 35xxA
3. Specifications 3.1. Outline Dimensions
PRELIMINARY DATA SHEET
1+0.2 x 45 9 1 61 0.457
0.9
2.4
16 x 1.27 0.1 = 20.32 0.1 1.27 0.1 1.2 x 45 2.4 1.27 0.1 15 24.2 0.1 27 26 0.4 0.2 4 0.1 15.6 0.1 14 0.1 0.3 3.2 0.2 0.24 0.27 0.06 0...15 2
10 2 9
60
9
26 27 25 +0.25 43
44 1.9 1.5 4.05 4.75 0.15
0.2
0.1
Fig. 3-1: 68-Pin Plastic Leaded Chip Carrier Package (PLCC68) Weight approximately 4.8 g Dimensions in mm
SPGS7004-3/4E
SPGS0016-4/2E
SPGS0015-1/2E
64 2.5
33
52
1
32 3.8 0.1
3
1
57.7 0.1 (1)
19.3 0.1 18 0.1 4.8 0.4 0.3
47 0.1
3.2 0.4
1.9
0.27 0.06 1.778 0.05 0.457 0.3 1 0.1 31 x 1.778 = 55.118 0.1 20.1 0.6 1 0.1 0.457 1.778 0.05 25 x 1.778 = 44.47 0.1
1.29
Fig. 3-2: 64-Pin Plastic Shrink Dual-Inline-Package (PSDIP64) Weight approximately 9.0 g Dimensions in mm
Fig. 3-3: 52-Pin Plastic Shrink Dual-Inline-Package (PSDIP52) Weight approximately 5.5 g Dimensions in mm
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16 x 1.27 0.1 = 20.32 0.1
0.711
25 +0.25
23.4
24.2 0.1
PRELIMINARY DATA SHEET
DPL 35xxA
X = obligatory; connect as described in circuit diagram AHVSS: connect to AHVSS 20/19: pin description valid for DPL 3520A and DPL 3519A 18: pin description valid for DPL 3518A Type Connection
(if not used)
3.2. Pin Connections and Short Descriptions NC = not connected; leave vacant LV = if not used, leave vacant DVSS: if not used, connect to DVSS Pin No.
PLCC 68-pin PSDIP 64-pin PSDIP 52-pin
Pin Name
Short Description
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
16 - 15 14 13 12 11 10 9 8 7 6 5 4 3 2 - 1 64 63 62 61 60 59 58 57 56 55
14 - 13 12 11 10 9 8 7 - 6 5 4 3 - - - 2 1 52 51 50 49 48 47 46 45 44
NC NC NC I2S_DA_IN1 I2S_DA_OUT1 I2S_WS I2S_CL I2C_DA I2C_CL NC STANDBYQ ADR_SEL D_CTR_IO0 D_CTR_IO1 NC NC NC AUD_CL_OUT D_CTR_IN XTAL_OUT XTAL_IN TESTEN NC NC NC AVSUP AVSS 20/19: MONO_IN 18: NC IN OUT IN OUT IN IN IN OUT OUT OUT IN/OUT IN IN IN IN IN/OUT IN/OUT
LV LV LV LV LV LV LV X X X X X LV LV LV LV LV LV LV X X X LV LV LV X X LV
Not connected Not connected Not connected I2S1 data input I2S1 data output I2S wordstrobe I2S clock I2C data I2C clock Not connected Standby (low-active) I2C-Bus address select Digital control IO 0 Digital control IO 1 Not connected Not connected Not connected Audio clock output Digital control input Crystal oscillator Crystal oscillator Test pin Not connected Not connected Not connected Analog power supply +5 V Analog ground Mono input
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PRELIMINARY DATA SHEET
Pin No.
PLCC 68-pin PSDIP 64-pin PSDIP 52-pin
Pin Name
Type
Connection
(if not used)
Short Description
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
54 53 52 51 50 49 48 47 46 - 45 44 43 42 41 40 39 38 37 36 35 34
43 42 41 - 40 39 - 38 37 - - - - 36 35 34 33 32 31 30 29 28
VREFTOP 20/19: SC1_IN_R 18: NC 20/19: SC1_IN_L 18: NC 20/19: ASG1 18: NC 20/19: SC2_IN_R 18: NC 20/19: SC2_IN_L 18: NC 20/19: ASG2 18: NC 20/19: SC3_IN_R 18: NC 20/19: SC3_IN_L 18: NC 20/19: ASG4 18: NC NC NC NC 20/19: AGNDC 18: NC 20/19: AHVSS 18: NC 20/19: CAPL_C1 18: NC 20/19: AHVSUP 18: NC 20/19: CAPL_C2 18: NC 20/19: SC1_OUT_L 18: NC 20/19: SC1_OUT_R 18: NC 20/19:VREF1 18: NC 20/19: SC2_OUT_L 18: NC OUT OUT OUT IN IN IN IN IN IN
X LV LV AHVSS LV LV AHVSS LV LV AHVSS LV LV LV X X X X X LV LV X LV
Reference voltage Scart input 1 in, right Scart input 1 in, left Analog Shield Ground 1 Scart input 2 in, right Scart input 2 in, left Analog Shield Ground 2 Scart input 3 in, right Scart input 3 in, left Analog Shield Ground 4 Not connected Not connected Not connected Analog reference voltage high voltage part Analog ground Volume capacitor Channel1 Analog power supply 8.0 V Volume capacitor Channel 2 Scart output 1, left Scart output 1, right Reference ground 1 high voltage part Scart output 2, left
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PRELIMINARY DATA SHEET
DPL 35xxA
Pin No.
PLCC 68-pin PSDIP 64-pin PSDIP 52-pin
Pin Name
Type
Connection
(if not used)
Short Description
51 - - 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
33 32 31 30 - - - 29 28 27 26 25 24 23 22 21 20 19 18 17
27 - - - - - - 25 24 23 22 21 20 - - 19 18 17 16 15
20/19: SC2_OUT_R 18: NC NC NC 20/19: ASG3 18: NC NC NC NC 20/19: DACC1_L 18: NC 20/19: DACC1_R 18: NC 20/19:VREF2 18: NC 20/19: DACC2_L 18: NC 20/19: DACC2_R 18: NC RESETQ NC NC I2S_DA_OUT2 I2S_DA_IN2 DVSS DVSUP NC
OUT
LV LV LV AHVSS LV LV LV
Scart output 2, right Not connected Not connected Analog Shield Ground 3 Not connected Not connected Not connected Analog output Channel 1, left Analog output Channel 1, right Reference ground 2 high voltage part Analog output Channel 2, left Analog output Channel 2, right Power-on-reset Not connected Not connected I2S2-data output I2S2-data input Digital ground Digital power supply +5 V Not connected
OUT OUT
LV LV X
OUT OUT IN
LV LV X LV LV
OUT IN
LV LV X X LV
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3.3. Pin Configurations
NC NC NC I2S_DA_IN1 I2S_DA_OUT1 I2S_WS I2S_CL I2C_DA I2C_CL NC DVSUP DVSS I2S_DA_IN2 I2S_DA_OUT2 NC NC RESETQ
PRELIMINARY DATA SHEET
NC STANDBYQ ADR_SEL D_CTR_IO0 D_CTR_IO1 NC NC NC AUD_CL_OUT D_CTR_IN XTAL_OUT XTAL_IN TESTEN NC NC NC AVSUP
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
9
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53
DACC2_R DACC2_L VREF2 DACC1_R DACC1_L NC NC NC ASG3 SC2_OUT_R SC2_OUT_L VREF1 SC1_OUT_R SC1_OUT_L CAPL_C2 AHVSUP CAPL_C1
DPL 3520A DPL 3519A
52 51 50 49 48 47 46 45 44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
AVSS MONO_IN VREFTOP SC1_IN_R SC1_IN_L ASG1 SC2_IN_R SC2_IN_L ASG2 NC ASG4 SC3_IN_L SC3_IN_R NC NC
AHVSS AGNDC
Fig. 3-4: 68-pin PLCC package of the DPL 3519A and DPL 3520A
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PRELIMINARY DATA SHEET
DPL 35xxA
NC
NC NC I2S_DA_IN1 I2S_DA_OUT1 I2S_WS I2S_CL I2C_DA I2C_CL
NC DVSUP DVSS I2S_DA_IN2 I2S_DA_OUT2 NC NC RESETQ
NC STANDBYQ ADR_SEL D_CTR_IO0 D_CTR_IO1 NC NC NC AUD_CL_OUT D_CTR_IN XTAL_OUT XTAL_IN TESTEN NC NC NC AVSUP
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
9
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53
NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
DPL 3518A
52 51 50 49 48 47 46 45 44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
AVSS NC VREFTOP NC NC NC NC NC NC NC NC NC NC NC NC NC
NC
Fig. 3-5: 68-pin PLCC package of the DPL 3518A
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PRELIMINARY DATA SHEET
AUD_CL_OUT NC NC D_CTR_IO1 D_CTR_IO0 ADR_SEL STANDBYQ NC I2C_CL I2C_DA I2S_CL I2S_WS I2S_DA_OUT1 I2S_DA_IN1 NC NC NC DVSUP DVSS I2S_DA_IN2 I2S_DA_OUT2 NC NC RESETQ DACC2_R DACC2_L VREF2 DACC1_R DACC1_L ASG3 NC NC
1 2 3 4 5 6 7 8 9 10 11
64 63 62 61 60 59 58 57 56 55 54
D_CTR_IN XTAL_OUT XTAL_IN TESTEN NC NC NC AVSUP AVSS MONO_IN VREFTOP SC1_IN_R SC1_IN_L ASG1 SC2_IN_R SC2_IN_L ASG2 SC3_IN_R SC3_IN_L NC NC NC AGNDC AHVSS CAPL_C1 AHVSUP CAPL_C2 SC1_OUT_L SC1_OUT_R VREF1 SC2_OUT_L SC2_OUT_R
AUD_CL_OUT NC NC D_CTR_IO1 D_CTR_IO0 ADR_SEL STANDBYQ NC I2C_CL I2C_DA I2S_CL I2S_WS I2S_DA_OUT1 I2S_DA_IN1 NC NC NC DVSUP DVSS I2S_DA_IN2 I2S_DA_OUT2 NC NC RESETQ NC NC NC NC NC NC NC NC
1 2 3 4 5 6 7 8 9 10 11 12
64 63 62 61 60 59 58 57 56 55 54 53
D_CTR_IN XTAL_OUT XTAL_IN TESTEN NC NC NC AVSUP AVSS NC VREFTOP NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
DPL 3520 /19 A
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
DPL 3518 A
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
Fig. 3-6: 64-pin PSDIP package of the DPL 3519A and DPL 3520A
Fig. 3-7: 64-pin PSDIP package of the DPL 3518A
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PRELIMINARY DATA SHEET
DPL 35xxA
D_CTR_IN AUD_CL_OUT D_CTR_IO0 D_CTR_IO1 ADR_SEL STANDBYQ I2C_CL I2C_DA I2S_CL I2S_WS I2S_DA_OUT1 I2S_DA_IN1 NC NC NC DVSUP DVSS I2S_DA_IN2 I2S_DA_OUT2 RESETQ DACC2_R DACC2_L VREF2 DACC1_R DACC1_L NC
1 2 3 4 5 6 7 8
52 51 50 49 48 47 46 45
XTAL_OUT XTAL_IN TESTEN NC NC NC AVSUP AVSS MONO_IN VREFTOP SC1_IN_R SC1_IN_L SC2_IN_R SC2_IN_L SC3_IN_R SC3_IN_L AGNDC AHVSS CAPL_C1 AHVSUP CAPL_C2 SC1_OUT_L SC1_OUT_R VREF1 SC2_OUT_L SC2_OUT_R
D_CTR_IN AUD_CL_OUT D_CTR_IO0 D_CTR_IO1 ADR_SEL STANDBYQ I2C_CL I2C_DA I2S_CL I2S_WS I2S_DA_OUT1 I2S_DA_IN1 NC NC NC DVSUP DVSS I2S_DA_IN2 I2S_DA_OUT2 RESETQ NC NC NC NC NC NC
1 2 3 4 5 6 7 8 9
52 51 50 49 48 47 46 45 44
XTAL_OUT XTAL_IN TESTEN NC NC NC AVSUP AVSS NC VREFTOP NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
DPL 3520/19 A
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
DPL 3518 A
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
Fig. 3-8: 52-pin PSDIP package of the DPL 3519A and DPL 3520A
Fig. 3-9: 52-pin PSDIP package of the DPL 3518A
3.4. Pin Circuits (pin numbers refer to PLCC68 package) DVSUP P N GND Fig. 3-10: Output Pins 5 and 64 (I2S_DA_OUT1/2) Fig. 3-12: Input Pins 4, 11, 12, 19, 61, 62, and 65 (I2S_DA_IN1/2, STANDBYQ, ADR_SEL, D_CTR_IN, RESETQ, TESTEN)
DVSUP P N GND Fig. 3-11: Input/Output Pins 8 and 9 (I2C_DA, I2C_CL) GND Fig. 3-13: Input/Output Pins 6, 7, 13, and 14 (I2S_WS, I2S_CL, D_CTR_IO0/1)
N
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PRELIMINARY DATA SHEET
P
40 K 3.75 V
3-30 pF
500 k
N
2.5 V
Fig. 3-18: Input Pins 30, 31, 33, 34, 36, and 37 (SC1-3_IN_L/R)
3-30 pF
AHVSUP
0...1.2 mA
Fig. 3-14: Output/Input Pins 18, 20, and 21 (AUD_CL_OUT, XTALIN/OUT)
3.3 K
VREFTOP
Fig. 3-19: Output Pins 56, 57, 59, and 60 (DACC1_L/R, DACC2_L/R)
Fig. 3-15: Pin 29 (VREFTOP)
125 K 3.75 V
Fig. 3-20: Pin 42 (AGNDC)
16 K 3.75 V
Fig. 3-16: Input Pin 28 (MONO_IN)
40 pF 80 K
300 3.75 V
0...2 V
Fig. 3-17: Capacitor Pins 44 and 46 (CAPL_C1, CAPL_C2)
Fig. 3-21: Output Pins 47, 48, 50 and 51 (SC_1/2_OUT_L/R)
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PRELIMINARY DATA SHEET
DPL 35xxA
3.5. Electrical Characteristics 3.5.1. Absolute Maximum Ratings Symbol TA TS VSUP1 VSUP2 VSUP3 dVSUP23 PTOT VIdig IIdig VIana IIana IOana IOana ICana
1) 2) 3) 4)
Parameter Ambient Operating Temperature Storage Temperature First Supply Voltage Second Supply Voltage Third Supply Voltage Voltage between AVSUP and DVSUP Chip Power Dissipation PLCC68 without Heat Spreader Input Voltage, all Digital Inputs Input Current, all Digital Pins Input Voltage, all Analog Inputs Input Current, all Analog Inputs Output Current, all SCART Outputs Output Current, all Analog Outputs except SCART Outputs Output Current, other pins connected to capacitors
Pin Name - - AHVSUP DVSUP AVSUP AVSUP, DVSUP AHVSUP, DVSUP, AVSUP
Min. 0 -40 -0.3 -0.3 -0.3 -0.5
Max. 70 125 9.0 6.0 6.0 0.5
Unit C C V V V V
1100 -0.3 VSUP2+0.3 +20 VSUP1+0.3 +5
3), 4) 3)
mW V mA1) V mA1)
- SCn_IN_s,2) MONO_IN SCn_IN_s,2) MONO_IN SCn_OUT_s2) DACp_s2) CAPL_p,2) AGNDC
-20 -0.3 -5
3), 4) 3)
3)
3)
positive value means current flowing into the circuit "n" means "1", "2" or "3", "s" means "L" or "R", "p" means "C1" or "C2" The Analog Outputs are short circuit proof with respect to First Supply Voltage and Ground. Total chip power dissipation must not exceed absolute maximum rating.
Stresses beyond those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions/Characteristics" of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
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3.5.2. Recommended Operating Conditions at TA = 0 to 70 C Symbol VSUP1 VSUP2 VSUP3 VREIL VREIH tREIL VDIGIL VDIGIH tSTBYQ1 Parameter First Supply Voltage Second Supply Voltage Third Supply Voltage RESET Input Low Voltage RESET Input High Voltage RESET Low Time after DVSUP Stable and Oscillator Startup Digital Input Low Voltage STANDBYQ, ADR_SEL, TESTEN, TESTEN D_CTR_IN, D_CTR_IO_0/1 STANDBYQ, DVSUP Pin Name AHVSUP DVSUP AVSUP RESETQ 0.8 5 Min. 7.6 4.75 4.75
PRELIMINARY DATA SHEET
Typ. 8.0 5.0 5.0
Max. 8.4 5.25 5.25 0.45
Unit V V V VSUP2 VSUP2 s
0.25
VSUP2 VSUP2 s
Digital Input High Voltage
0.75
STANDBYQ Setup Time before Turn-off of Second Supply Voltage
1
I2C-Bus Recommendations VIMIL VIMIH fIM tI2C1 tI2C2 tI2C3 tI2C4 tI2C5 tI2C6 VI2SIL VI2SIH tI2S1 tI2S2 I2C-BUS Input Low Voltage I2C-BUS Input High Voltage I2C-BUS Frequency I2C START Condition Setup Time I2C STOP Condition Setup Time I2C-Clock Low Pulse Time I2C-Clock High Pulse Time I2C-Data Setup Time Before Rising Edge of Clock I2C-Data Hold Time after Falling Edge of Clock I2S-Data Input Low Voltage I2S-Data Input High Voltage I2S-Data Input Setup Time before Rising Edge of Clock I2S-Data Input Hold Time after Falling Edge of Clock I2S_DA_IN1/2, I2S_CL I2S_DA_IN1/2 0.75 20 0 I2C_CL, I2C_DA I2C_CL, C_DA I2C DA 0.6 I2C_CL I2C_CL, C_DA I2C DA I2C_CL 120 120 500 500 55 55 0.25 1.0 0.3 VSUP2 VSUP2 MHz ns ns ns ns ns ns VSUP2 VSUP2 ns ns
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PRELIMINARY DATA SHEET
DPL 35xxA
Symbol VI2SIDL VI2SIDH fI2SCL
Parameter I2S-Input Low Voltage when DPL 3520/19/18A in I2S-Slave-Mode I2S-Input High Voltage when DPL 3520/19/18A in I2S-Slave-Mode I2S-Clock Input Frequency when DPL 3520/19/18A in I2S-SlaveMode I2S-Clock Input Ratio when DPL 3520/19/18A in I2S-SlaveMode I2S-Wordstrobe Input Frequency when DPL 3520/19/18A in I2SSlave-Mode I2S-Wordstrobe Input Setup Time before Rising Edge of Clock when DPL 3520/19/18A in I2S-SlaveMode I2S-Wordstrobe Input Hold Time after Falling Edge of Clock when DPL 3520/19/18A in I2S-SlaveMode
Pin Name I2S_CL, I2S_WS
Min.
Typ.
Max. 0.25
Unit VSUP2 VSUP2
0.75 I2S_CL 1.024
MHz
RI2SCL
0.9
1.1
MHz
fI2SWS
I2S_WS
32.0
kHz
tI2SWS1
I2S_WS, I2S_CL
60
ns
tI2SWS2
0
ns
Crystal Recommendations for Master-Slave Application fP fTOL DTEM RR C0 C1 Parallel Resonance Frequency at 12 pF Load Capacitance Accuracy of Adjustment Frequency Variation versus Temperature Series Resistance Shunt (Parallel) Capacitance Motional (Dynamic) Capacitance 19 -20 -20 8 6.2 24 18.432 +20 +20 25 7.0 MHz ppm ppm pF fF
Load Capacitance Recommendations for Master-Slave Applications CL fCL External Load Capacitance2) Required Open Loop Clock Frequency (Tamb = 25C) XTAL_IN, XTAL_OUT PSDIP PLCC 18.431 1.5 3.3 18.433 pF pF MHz
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PRELIMINARY DATA SHEET
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Crystal Recommendations for Stand Alone Application (No Master-Slave Mode possible) fP fTOL DTEM RR C0 Parallel Resonance Frequency at 12 pF Load Capacitance Accuracy of Adjustment Frequency Variation versus Temperature Series Resistance Shunt (Parallel) Capacitance -100 -50 8 6.2 18.432 +100 +50 25 7.0 MHz ppm ppm pF
Load Capacitance Recommendations for Stand Alone Application (No Master-Slave Mode possible) CL External Load Capacitance2) XTAL_IN, XTAL_OUT PSDIP PLCC 1.5 3.3 pF pF
Amplitude Recommendation for Operation with External Clock Input (Cload after reset = 22 pF) VXCA External Clock Amplitude XTAL_IN 0.7 Vpp
Analog Input and Output Recommendations CAGNDC AGNDC-Filter-Capacitor Ceramic Capacitor in Parallel CinSC VinSC VinMONO RLSC CLSC CVMA CFMA CVREFTOP
1) 2)
AGNDC
-20% -20%
3.3 100 330 +20% 2.0
F nF nF VRMS VRMS k 7.5 nF F +10% nF F
DC-Decoupling Capacitor in front of SCART Inputs SCART Input Level Input Level, Mono Input SCART Load Resistance SCART Load Capacitance Channel1/2 Volume Capacitor Channel1/2 Filter Capacitor VREFTOP-Filter-Capacitor
SCn_IN_s1)
-20%
MONO_IN SCn_OUT_s1) 10
2.0
CAPL_s1) DACp_s1) VREFTOP -10% -20%
10 1 10
"n" means "1", "2" or "3", "s" means "L" or "R", "p" means "C1" or "C2" External capacitors at each crystal pin to ground are required. They are necessary to tune the open-loop frequency of the internal PLL and to stabilize the frequency in closed-loop operation. The higher the capacitors, the lower the clock frequency results. The nominal free running frequency should match 18.432 MHz as closely as possible. Due to different layouts of customer PCBs, the matching capacitor size should be defined in the application. The suggested values (1.5 pF/3.3 pF) are figures based on experience with various PCB layouts.
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PRELIMINARY DATA SHEET
DPL 35xxA
3.5.3. Characteristics at TA = 0 to 70 C, fCLOCK = 18.432 MHz, VSUP1 = 7.6 to 8.4 V, VSUP2,3 = 4.75 to 5.25 V for min./max. values (Typical values are measured at TA = 25 C, AHVSUP = 8 V, DVSUP = 5 V, AVSUP = 5 V.)
Symbol DCO fCLOCK DCLOCK tJITTER VxtalDC tStartup Clock Input Frequency Clock High to Low Ratio Clock Jitter (verification not provided in production test) DC-Voltage Oscillator Oscillator Startup Time at VDD Slew-rate of 1 V / 1 s XTAL_IN, XTAL_OUT 2.5 0.4 1.0 XTAL_IN 45 18.432 55 50 MHz % ps Parameter Pin Name Min. Typ. Max. Unit Test Conditions
V ms
Power Supply ISUP1A First Supply Current (active)
Analog Volume for channel1/2 at 0dB Analog Volume for channel1/2 at -30dB
AHVSUP 8.2 5.6 14.8 10.0 22.0 15.0 mA mA
at Tj = 27 C ISUP2A ISUP3A ISUP1S
f = 18.432 MHz AHVSUP = 8 V DVSUP = 5 V AVSUP = 5 V f = 18.432 MHz DVSUP = 5 V f = 18.432 MHz AVSUP = 5 V STANDBYQ = low VSUP = 8 V
Second Supply Current (active)
DVSUP
60
65
70
mA
Third Supply Current (active)
AVSUP
25
mA
First Supply Current (standby mode) at Tj = 27 C
AHVSUP
2.8
5.0
7.2
mA
Audio Clock Output VAPUAC VAPUDC Digital Output VDCTROL VDCTROH I2C Bus VIMOL IIMOH tIMOL1 tIMOL2 I2C-Data Output Low Voltage I2C-Data Output High Current I2C-Data Output Hold Time after Falling Edge of Clock I2C-Data Output Setup Time before Rising Edge of Clock I2C_DA, I2C_CL 15 I2C_DA 0.4 1 V A ns IIMOL = 3 mA VIMOH = 5 V Digital Output Low Voltage Digital Output High Voltage D_CTR_IO0 D_CTR_IO1 D CTR IO1 4.0 0.4 V V IDDCTR = 1 mA IDDCTR = -1 mA Audio Clock Output AC Voltage Audio Clock Output DC Voltage AUD_CL_OUT 1.2 0.4 0.6 Vpp VSUP1 40 pF load
100
ns
fIM = 1 MHz DVSUP = 5 V
I2S Bus VI2SOL VI2SOH fI2SCL fI2SWS I2S Output Low Voltage I2S Output High Voltage I2S-Clock Output Frequency I2S-Wordstrobe Output Frequency I2S_WS, I2S_CL, I2S CL I2S_DA_OUT I2S_CL I2S_WS 0.4 4.0 1204 32.0 V V kHz kHz II2SOL = 1 mA II2SOH = -1 mA DVSUP = 5 V DVSUP = 5 V
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PRELIMINARY DATA SHEET
Symbol tI2S1/I2S2 tI2S3 tI2S4 tI2S5 tI2S6
Parameter I2S-Clock High/Low-Ratio I2S-Data Setup Time before Rising Edge of Clock I2S-Data Hold Time after Falling Edge of Clock I2S-Wordstrobe Setup Time before Rising Edge of Clock I2S-Wordstrobe Hold Time after Falling Edge of Clock
Pin Name I2S_CL I2S_CL, I2S_DA_OUT
Min. 0.9 200
Typ. 1.0
Max. 1.1
Unit
Test Conditions
ns
DVSUP = 4.75 V
12
ns
DVSUP = 5.25 V
I2S_CL, I2S_WS
100
ns
DVSUP = 4.75 V
50
ns
DVSUP = 5.25 V
Analog Ground VAGNDC0 RoutAGN AGNDC Open Circuit Voltage AGNDC Output Resistance at Tj = 27 C from TA = 0 to 70 C AGNDC 3.64 3.73 3.84 V Rload 10 M 3 V VAGNDC 4 V 70 70 125 180 180 k k
Analog Input Resistance RinSC SCART Input Resistance at Tj = 27 C from TA = 0 to 70 C MONO Input Resistance at Tj = 27 C from TA = 0 to 70 C SCn_IN_s1) 25 25 MONO_IN 10 10 16 23 23 k k 40 58 58 k k fsignal = 1 kHz, I 0.05 mA
RinMONO
fsignal = 1 kHz, I 0.1 mA
Audio Analog-to-Digital-Converter VAICL Analog Input Clipping Level for Analog-to-Digital-Conversion SCn_IN_s,1) MONO_IN 2.00 2.12 2.25 VRMS fsignal = 1 kHz
SCART Outputs RoutSC SCART Output Resistance at Tj = 27 C from TA = 0 to 70 C Deviation of DC-Level at SCART Output from AGNDC Voltage Gain from Analog Input to SCART Output Frequency Response from Analog Input to SCART Output bandwidth: 0 to 20000 Hz Signal Level at SCART-Output during full-scale digital input signal from DSP "s" means "L" or "R", SCn_IN_s1) MONO_IN SCn_OUT_s1) SCn_OUT_s1) 0.20 0.20 -70 0.33 0.46 0.5 +70 k k mV fsignal = 1 kHz, I = 0.1 mA
dVOUTSC ASCtoSC frSCtoSC
fsignal = 1kHz -1.0 0 +0.5 dB with respect to 1 kHz -0.5 0 +0.5 dB
VoutSC
SCn_OUT_s1)
1.8
1.9
2.0
VRMS
fsignal = 1 kHz
1)
"n" means "1", "2" or "3",
"p" means "C1" or "C2"
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PRELIMINARY DATA SHEET
DPL 35xxA
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
Channel 1 and 2 Outputs RoutMA Channel1/2 Output Resistance at Tj = 27 C from TA = 0 to 70 C DC-Level at Channel1/2-Output for Analog Volume at 0 dB for Analog Volume at -30 dB Signal Level at Channel1/2-Output during full-scale digital input signal from DSP for Analog Volume at 0 dB DACp_s1) 2.1 2.1 3.3 4.6 5.0 k k fsignal = 1 kHz, I = 0.1 mA
VoutDCMA
1.74 -
1.94 61
2.28 -
V mV
VoutMA
1.23
1.37
1.51
VRMS
fsignal = 1 kHz
Analog Performance SNR Signal-to-Noise Ratio from Analog Input to DSP MONO_IN, SCn_IN_s1) 85 88 dB Input Level = -20 dB with resp. to VAICL, fsig = 1 kHz, equally weighted 20 Hz ... 16 kHz2) Input Level = -20 dB, fsig = 1 kHz, equally weighted 20 Hz ... 20 kHz Input Level = -20 dB, fsig = 1 kHz, equally weighted 20 Hz ... 15 kHz3) Input Level = -20 dB, fsig = 1 kHz, equally weighted 20 Hz ... 15 kHz3)
from Analog Input to SCART Output
MONO_IN, SCn_IN_s1) SCn_OUT_s1) SCn_OUT_s1)
93
96
dB
from DSP to SCART Output
85
88
dB
from DSP to Channel1/2-Output for Analog Volume at 0 dB for Analog Volume at -30 dB
DACp_s1) 85 78 88 83 dB dB
THD
Total Harmonic Distortion from Analog Input to DSP MONO_IN, SCn_IN_s1) 0.05 % Input Level = -3 dBr with resp. to VAICL, fsig =1kHz, equally weighted 20 Hz ...16 kHz, RLoad = 30 k2) Input Level = -3 dBr, fsig = 1 kHz, equally weighted 20 Hz ... 20 kHz, RLoad = 30 k Input Level = -3 dBr, fsig = 1 kHz, equally weighted 20 Hz ... 16 kHz, RLoad = 30 k3) Input Level = -3 dBr, fsig = 1 kHz, equally weighted 20 Hz ... 16 kHz, RLoad = 30 k3)
from Analog Input to SCART Output
MONO_IN, SCn_IN_s SCn_OUT_s1) SCn_OUT_s1)
0.01
0.03
%
from DSP to SCART Output
0.01
0.03
%
from DSP to Channel1/2 Output
DACp_s1)
0.01
0.03
%
1) 2) 3)
"n" means "1", "2" or "3", "s" means "L" or "R", DSP measured at I2S-Output DSP Input at I2S-Input
"p" means "C1" or "C2"
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PRELIMINARY DATA SHEET
Symbol XTALK
Parameter Crosstalk attenuation - PLCC68 - PSDIP64
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions Input Level = -3 dB, fsig = 1 kHz, unused analog inputs connected to ground by Z<1 k equally weighted 20 Hz ... 20 kHz
between left and right channel within SCART Input/Output pair (LR, RL) SCn_IN SCn_OUT1) SCn_IN DSP1) DSP SCn_OUT1) PLCC68 PSDIP64 PLCC68 PSDIP64 PLCC68 PSDIP64 80 80 80 80 80 80 dB dB dB dB dB dB
2)
3)
between left and right channel within channel1/2 Output pair DSP DACp1) between SCART Input/Output pairs1) D = disturbing program O = observed program D: MONO/SCn_IN SCn_OUT O: MONO/SCn_IN SCn_OUT1) D: MONO/SCn_IN SCn_OUT O: or unsel. MONO/SCn_IN DSP1) D: MONO/SCn_IN SC1_OUT O: DSP SCn_OUT1) D: MONO/SCn_IN unselected O: DSP SC1_OUT1) PLCC68 PSDIP64 PLCC68 PSDIP64 PLCC68 PSDIP64 PLCC68 PSDIP64 100 100 95 95 100 100 100 100 dB dB dB dB dB dB dB dB PLCC68 PSDIP64 80 75 dB dB
equally weighted 20 Hz ... 16 kHz
3)
(equally weighted 20 Hz ... 20 kHz) same signal source on left and right disturbing channel, channel effect on each observed output channel
2)
3)
3)
Crosstalk between channel 1 and channel 2 Output pairs DSP DACp1) PLCC68 PSDIP64
95 90
dB dB
(equally weighted 20 Hz ... 16 kHz)3) same signal source on left and right disturbing channel, effect on each observed output channel (equally weighted 20 Hz ... 20 kHz) same signal source on g left and right disturbing channel, effect on each observed output channel
Crosstalk from channel 1 and channel 2 to SCART Output and vice versa D = disturbing program O = observed program D: MONO/SCn_IN/DSP SCn_OUT O: DSP DACp1) D: MONO/SCn_IN/DSP SCn_OUT O: DSP DACp1) D: DSP DACp O: MONO/SCn_IN SCn_OUT1) D: DSP DACp O: DSP SCn_OUT1)
1) 2) 3)
PLCC68 PSDIP64 PLCC68 PSDIP64 PLCC68 PSDIP64 PLCC68 PSDIP64
90 85 95 85 100 95 100 95
dB dB dB dB dB dB dB dB
SCART output load resistance 10 k SCART output load resistance 30 k
3)
"n" means "1", "2" or "3", "s" means "L" or "R", DSP measured at I2S-Output DSP Input at I2S-Input
"p" means "C1" or "C2"
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PRELIMINARY DATA SHEET
DPL 35xxA
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
PSRR: rejection of noise on AHVSUP at 1 kHz PSRR AGNDC From analog Input to DSP AGNDC MONO_IN SCn_IN_s1) MONO_IN SCn_IN_s,1) SCn_OUT_s1) SCn_OUT_s1) DACp_s1) "p" means "C1" or "C2" 80 69 dB dB
From analog Input to SCART Output
74
dB
From DSP to SCART Output From DSP to channel1/2 Output
1)
70 80
dB dB
"n" means "1", "2" or "3",
"s" means "L" or "R",
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DPL 35xxA
3.5.4. Measurements According to Dolby Specifications, Typical Values
PRELIMINARY DATA SHEET
(Typical values are measured at TA = 25 C, AHVSUP = 8 V, DVSUP = 5 V, AVSUP = 5 V.)
Crosstalk at cardinal point at High Level Input (+15 dB @ 1 kHz = 0 dB Full Scale = 2 Vrms) Channel Left: Center: Right: Surround: L +0.17 -53 -68 -56 C -60 0.0 -62 -70 R -68 -53 +0.03 -56 S -57 -63 -60 +0.02
Crosstalk at cardinal point at Low Level Input (-20dB @ 1kHz = -35dBdB Full Scale) Channel Left: Center: Right: Surround: L +0.08 -45 -45 -39 C -44 0.0 -44 -44 R -46 -46 0.05 -44 S -41 -41 -41 -2.58
Frequency Response Characteristics Mode Normal Wide Phantom L 20/15.4k 20/15.4k 20/15.4k C 100/15.4k 20/15.4k ---------- R 20/15.4k 20/15.4k 20/15.4k S 20/7k 20/7k 20/7k
SNR Measurements L Weighted -69dB C -69dB R -69dB S -69dB
Measured on the Dolby Stand Alone Board. Conditions: 355 mVrms @ SCART1IN with 2 kHz Scart Prescale = 20 h, Vol = -9 dB 100 mVrms output @DAC1out measured with CCIR/ARM (System One: CCIR-2k, AVG) 26 Micronas
PRELIMINARY DATA SHEET
DPL 35xxA
done by sending the device read address (81 hex, 85 hex, or 89 hex) and reading two bytes of data. Refer to Fig. 4-1: I2C-Bus Protocol and section 4.2.: Proposal for DPL I2C-Telegrams. Due to the internal architecture of the DPL, the IC cannot react immediately to an I2C request. The typical response time is about 0.3 ms. If the receiver (DPL) cannot receive another complete byte of data until it has performed some other function, it can hold the clock line I2C_CL LOW to force the transmitter into a wait state. The positions within a transmission where this may happen are indicated by `Wait' in section 4.1. The maximum wait period of the DPL during normal operation mode is less than 1 ms. I2C-Bus error conditions: If an internal error occurs, the DPLs wait period is extended to a maximum of 1.8 ms. Afterwards, the DPL does not acknowledge (NAK) the device address. The data line will be left HIGH by the DPL and the clock line will be released. The master can then generate a STOP condition to abort the transfer. By means of NAK, the master is able to recognize the error state and to reset the IC via I2C-Bus. While transmitting the reset protocol (see 4.1.) to `CONTROL', the master must ignore the `Not Acknowledge Bits' (NAK) of the DPL.
4. I2C-Bus Interface As a slave receiver, the DPL can be controlled via I2Cbus. Access to internal memory locations is achieved by subaddressing. The MODE_REG, the CONTROL register and the DFP processor have separate subaddressing register banks. In order to allow for more DPL or MSP ICs to be connected to the control bus, an ADR_SEL pin was implemented. With ADR_SEL pulled to high, low, or left open, the DPL responds to changed device addresses. Thus, three identical devices can be selected. By means of the RESET bit in the CONTROL register, all devices with the same device address are reset. The IC is selected by asserting a special device address in the address part of an I2C-transmission. A device address pair is defined as a write address (80 hex, 84 hex, or 88 hex) and a read address (81 hex, 85 hex, or 89 hex). Writing is done by sending the device write address first, followed by the subaddress byte, two address bytes, and two data bytes. For reading, the read address has to be transmitted first by sending the device write address (80 hex, 84 hex, or 88 hex), followed by the subaddress byte and two address bytes. Without sending a stop condition, reading of the addressed data is
Table 4-1: I2C-Bus Device and Subaddresses Name Binary Value Hex Value Hex Value ADR_SEL= high 84/85 00 10 11 12 13 Hex Value Mode Function
low DPL CONTROL WR_MR RD_MD WR_DFP RD_DFP 1000 xx0x 0000 0000 0001 0000 0001 0001 0001 0010 0001 0011 80/81
left open 88/89 R/W W W W W W DPL device address software reset write address MODE_REG read address MODE_REG write address DFP read address DFP
Table 4-2: Control Register Name CONTROL MSB RESET 14 0 13..1 0 LSB 0
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4.1. Protocol Description Write to DFP or MODE_REG
S hex 80 Wait ACK sub-addr ACK addr-byte high ACK addr-byte low ACK
PRELIMINARY DATA SHEET
data-byte high
ACK
data-byte low
ACK
P
Read from DFP or MODE_REG
S hex 80 Wait ACK sub-addr ACK addr-byte high ACK addr-byte low ACK S hex 81 Wait ACK data-byte high
Write to the Control Register
S hex 80 Wait ACK sub-addr ACK data-byte high ACK
data-byte low
Note: S = P= ACK = NAK = Wait =
I2C-Bus Start Condition from master I2C-Bus Stop Condition from master Acknowledge-Bit: LOW on I2C_DA from slave (= DPL, grey) or master (= CCU, hatched) Not Acknowledge-Bit: HIGH on I2C_DA from master (= CCU, hatched) to indicate `End of Read' or from DPL indicating internal error state I2C-Clock line held low by the slave (= DPL) while interrupt is serviced (<1 ms)
I2C_DA S I2C_CL Fig. 4-1: I2C-bus protocol
1 0
P
(MSB first; data must be stable while clock is high)
4.2. Proposal for DPL I2C-Telegrams
4.2.3. Read Telegrams
read data from MODE_REG
4.2.1. Symbols daw dar < > aa dd Write Device Address Read Device Address Start Condition Stop Condition Address Byte Data Byte
register
read data from DFP register
4.2.4. Examples
<80 00 80 00> <80 00 00 00> <80 12 00 08 03 20>
RESET DPL statically clear RESET set channel source 1 to DOLBYLR and Matrix to STEREO
4.2.2. Write Telegrams

software RESET write data into MODE_REG register write data into DFP register
4.3. Start-Up Sequence After power on or RESET, the IC is in an inactive state. The CCU has to transmit the required coefficient set for a given operation via the I2C-bus. Micronas
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CCC CCC CCC CCC
ACK data-byte low NAK P ACK P
PRELIMINARY DATA SHEET
DPL 35xxA
6. I2S-Bus Interface By means of this standardized interface, additional feature processors can be connected to the DPL. Two possible formats are supported: The standard mode (MODE_REG[4]=0) selects the SONY format, where the I2S_WS signal changes at the word boundaries. The so-called PHILIPS format, which is characterized by a change of the I2S_WS signal one I2S_CL period before the word boundaries, is selected by setting MODE_REG[4]=1. The DPL normally serves as the slave on the I2S interface (default setting after power-up). I2S-clock and word strobe lines are input to the DPL and the master clock is synchronized to 576 times the I2S_WS rate (32 kHz). By setting MODE_REG[3]=0, the DPL is switched to Master Mode. Now, these lines are input to the DPL and the master clock is synchronized to 576 times the I2S_WS rate (32 kHz). The I2S-bus interface consists of six pins: 1. I2S_DA_IN1, I2S_DA_IN2: For input, four channels (two channels per line, 2 16 bits) per sampling cycle (32 kHz) are transmitted. 2. I2S_DA_OUT1, I2S_DA_OUT2: For output, four channels (two channels per line, 2 16 bits) per sampling cycle (32 kHz) are transmitted. 3. I2S_CL: Gives the timing for the transmission of I2S serial data (1.024 MHz). 4. I2S_WS: The I2S_WS word strobe line defines the left and right sample.
5. Audio PLL and Crystal Specifications 5.1. Operation with Crystal The DPL requires a 18.432 MHz (12 pF, parallel) crystal. The clock supply of the whole system depends on the DPL operation mode: 1. Stand-Alone The system clock runs free on the crystal's 18.432 MHz. 2. I2S slave operation: In this case, the system clock is locked to a synchronizing signal (I2S_WS) supplied by the coprocessor chip. Remark on using the crystal: External capacitors are required at each crystal pin to ground. They are necessary for tuning the open-loop frequency of the internal PLL and for stabilizing the frequency in closed-loop operation. The higher the capacitors, the lower the clock frequency results. The nominal free running frequency should match the center of the tolerance range between 18.433 and 18.431 MHz as closely as possible. 5.2. Operation without Crystal When used together with a member of the MSP family, the DPL can be driven by the 18.432 MHz clock supplied by the MSP. The clock input is: XTAL_IN (connection via coupling capacitor (C>1nF)). No crystal is used in this mode.
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DPL 35xxA
6.1. I2S Bus Timing Diagram
FI2SWS I2S_WS
PRELIMINARY DATA SHEET
SONY Mode PHILIPS Mode PHILIPS/SONY Mode programmable by MODE_REG[4] I2S_CL Detail A I2S_DAIN
R LSB L MSB
SONY Mode PHILIPS Mode Detail C
L LSB R MSB
R LSB L LSB
16 bit left channel Detail B I2S_DAOUT
R LSB L MSB L LSB R MSB
16 bit right channel
R LSB L LSB
16 bit left channel
16 bit right channel
Detail C
I2S_CL
FI2SCL
TI2SWS1
TI2SWS2
I2S_WS as INPUT TI2S5 TI2S6
I2S_WS as OUTPUT
Detail A,B
I2S_CL
TI2S1
TI2S2
I2S_DA_IN TI2S3 TI2S4
I2S_DA_OUT
30
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PRELIMINARY DATA SHEET
DPL 35xxA
7. Power-up Sequence The reset pin should not be high (> 0.45 DVSUP, see recommended operation conditions) before the 5 Volt digital powersupply (DVSUP) is > 4.75 Volt and the DPL-Clock is running (Delay: 1 ms max, 0.5 ms typ.). This means, if the reset low-high edge starts with a delay of 2 ms after DVSUP> 4.75 Volt, even under worst case conditions, the reset is ok. First Supply Voltage DVSUP/V 4.75
time / ms Oscillator max. 1
time / ms RESETQ min. 2
0.45 * DVSUP
time / ms Fig. 7-1: Power-up sequence
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DPL 35xxA
8. Programming the Mode Register All transmissions on the control bus are 16 bits wide. Table 8-1: DPL mode register Register Write Address (hex) 0083 Function
PRELIMINARY DATA SHEET
MODE_REG
mode register
The register `MODE_REG' contains the control bits determining the operation mode of the DPL; Table 8-2 explains all bit positions. Table 8-2: Control word `MODE_REG' MODE_REG 0083hex Bit Function Comment Definition Reset condition 0 Digital control IO 0/1 tristate I2S outputs tristate (I2S_CL, I2S_WS, I2S_DA_OUT) Master/Slave mode of the I2S-bus WS due to the Sony or Philips-Format Switch Audio_Clock_Output to tristate 0 : active 1 : tristate 0 : active 1 : tristate 0 : Master 1 : Slave 0 : Sony 1 : Philips 0 : on 1 : tristate 1 1 Recommendation 0 0 0
[0] [1] [2]
not used DCTR_TRI I2S_TRI
[3] [4] [5] [15:6]
I2S_MODE I2S_WS_MODE AUDIO_CL_OUT not used
1 0 0 0
X X X 0
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PRELIMINARY DATA SHEET
DPL 35xxA
9. Programming the DSP Part 9.1. Summary of the DSP Control Registers Control registers are 16 bits wide. Transmissions via I2C-bus have to take place in 16-bit words. Single data entries are 8-bit. Some of the defined 16-bit words are divided into low and high byte, thus holding two different control entities. All control registers are readable. Note: Unused parts of the 16-bit registers must be zero. Table 9-1: Summary of the DSP Control Registers
Name I2C Bus Address High Adjustable Range, Operational /Low Modes Reset Mode Valid for
Standard MSP like Control Registers Volume channel 1 Volume / Mode channel 1 Balance channel 1 [L/R] Balance Mode channel 1 Bass channel 1 Treble channel 1 Loudness channel 1 Loudness Filter Characteristic Spatial effect strength channel 1 Spatial effect mode/customize Volume channel 2 Volume / Mode channel 2 Volume SCART channel Volume / Mode SCART channel Channel 1 source Channel 1 matrix Channel 2 source Channel 2 matrix SCART channel source SCART channel matrix I2S1 channel source I2S1 channel matrix Quasi-peak detector source 000chex 000bhex 000ahex 0009hex 0008hex 0007hex 0006hex 0005hex 0002hex 0003hex 0004hex 0001hex 0000hex H L H L H H H L H L H L H L H L H L H L H L H [+12 dB ... -114 dB, MUTE] 1/8 dB Steps, Reduce Volume / Tone Control [0..100 / 100 % and vv][-127..0 / 0 dB and vv] [Linear mode / logarithmic mode] [+20 dB ... -12 dB] [+15 dB ... -12 dB] [0 dB ... +17 dB] [NORMAL, SUPER_BASS] [-100%...OFF...+100%] [SBE, SBE+PSE] [+12 dB ... -114 dB, MUTE] 1/8 dB Steps, Reduce Volume / Tone Control [00hex ... 7Fhex],[+12 dB ... -114 dB, MUTE] [Linear mode / logarithmic mode] [SCART, DOLBYLR, DOLBYCS, DOLBYCSUB, I2S1, I2S2] [SOUNDA, SOUNDB, STEREO, MONO...] [SCART, DOLBYLR, DOLBYCS, DOLBYCSUB, I2S1, I2S2] [SOUNDA, SOUNDB, STEREO, MONO...] [SCART, DOLBYLR, DOLBYCS, DOLBYCSUB, I2S1, I2S2] [SOUNDA, SOUNDB, STEREO, MONO...] [SCART, DOLBYLR, DOLBYCS, DOLBYCSUB, I2S1, I2S2] [SOUNDA, SOUNDB, STEREO, MONO...] MUTE 00hex
100%/100%
19/20 19/20 19/20 19/20 19/20 19/20 19/20 19/20 19/20 19/20 19/20 19/20 19/20 19/20 19/20 19/20 19/20 19/20 19/20 19/20 all all all
linear mode 0 dB 0 dB 0 dB NORMAL OFF SBE+PSE MUTE 00hex 00hex linear mode 00hex
(undefined source)
SOUNDA 00hex
(undefined source)
SOUNDA 00hex
(undefined source)
SOUNDA 00hex
(undefined source)
SOUNDA 00hex
EE EEEE E E E E EE EEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE E E E EEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE E E E
[SCART, DOLBYLR, DOLBYCS, DOLBYCSUB, I2S1, I2S2]
(undefined source)
Micronas
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DPL 35xxA
PRELIMINARY DATA SHEET
Name Quasi-peak detector matrix Prescale SCART Prescale I2S2 ACB Register (SCART Switches and DIG_OUT Pins) Beeper Prescale I2S1 Mode Tone Control*)
I2C Bus Address
High Adjustable Range, Operational /Low Modes L [SOUNDA, SOUNDB, STEREO, MONO...] [00hex ... 7Fhex] [00hex ... 7Fhex] Bits [7..0] [00hex ... 7Fhex]/[00hex ... 7Fhex] [00hex ... 7Fhex] [BASS/TREBLE, EQUALIZER] [)12 dB ... *12 dB] [)12 dB ... *12 dB] [)12 dB ... *12 dB] [)12 dB ... *12 dB] [)12 dB ... *12 dB] [0...100 / 100% and vv][-127...0 / 0 dB and vv] [Linear mode / logarithmic mode] [+20 dB ... -12 dB] [+15 dB ... -12 dB] [0 dB ... +17 dB] [NORMAL, SUPER_BASS] [SCART, DOLBYLR, DOLBYCS, DOLBYCSUB, I2S1, I2S2] [SOUNDA, SOUNDB, STEREO, MONO...]
Reset Mode SOUNDA 00hex 10hex 00hex 0/0 10hex BASS/TREB 0dB 0dB 0dB 0dB 0dB
100%/100%
Valid for all 20 all 19/20 19/20 all 19(/20)*) 19(/20)*) 19(/20)*) 19(/20)*) 19(/20)*) 19(/20)*) 19/20 19/20 19/20 19/20 19/20 19/20 all all
000dhex 0012hex 0013hex 0014hex 0016hex 0020hex 0021hex 0022hex 0023hex 0024hex 0025hex 0030hex
H H H H/L H H H H H H H H L
Equalizer channel 1 band 1*) Equalizer channel 1 band 2*) Equalizer channel 1 band 3*) Equalizer channel 1 band 4*) Equalizer channel 1 band 5*) Balance channel 2 [L/R] Balance Mode channel 2 Bass channel 2 Treble channel 2 Loudness channel 2 Loudness filter characteristic I2S2 channel source I2S2 channel matrix
linear mode 0 dB 0 dB 0 dB NORMAL 00hex
(undefined source)
0031hex 0032hex 0033hex
H H H L
0038hex
H L
SOUNDA
Surround Processing Control Registers Surround decoder mode Surround reproduction mode 0040hex H L [ADAPTIVE, PASSIVE, EFFECT] [NORMAL, PHANTOM, WIDE, DOLBY_3_STEREO, CENTER_OFF, PANORAMA] [SCART, I2S1, I2S2, NOISE] [SOUNDA, SOUNDB, STEREO, NOISEL, NOISER, NOISEC, NOISES] [0..31 ms] [*12..)12 dB] [AUTOMATIC, MANUAL] [0..100%] [0..100%] [0..100%] ADAPTIVE NORMAL all all
Surround source Surround source matrix Surround delay Surround input balance control Input balance mode Surround spatial effect Panorama sound effect Surround reverberation
0041hex
H L
00hex
(undefined source)
all all all all all all all all
SOUNDA 0 0 AUTOMATIC 00hex 00hex 00hex
0042hex 0043hex 0043hex 0044hex 0045hex 0046hex
H H L H H H
*) Equalizing function only for SOUNDA (=Center) possible. Equalizer and AD input cannot work simultaneously. In the DPL 3520A
the equalizer can only be used in coprocessor mode (input via I2C and not via AD converter).
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PRELIMINARY DATA SHEET
DPL 35xxA
If the clipping mode is set to "Reduce Volume", the following clipping procedure is used: To prevent severe clipping effects with bass, treble, or equalizer boosts, the internal volume is automatically limited to a level where, in combination with either bass, treble, or equalizer setting, the amplification does not exceed 12 dB. If the clipping mode is "Reduce Tone Control", the bass or treble value is reduced if amplification exceeds 12 dB. If the equalizer is switched on, the gain of those bands is reduced, where amplification together with volume exceeds 12 dB. If the clipping mode is "Compromise Mode", the bass or treble value and volume are both reduced by half, if amplification exceeds 12 dB. If the equalizer is switched on, the gain of those bands is reduced by half, where amplification together with volume exceeds 12 dB.
9.1.1. Volume Channel 1 and Channel 2 Volume Channel 1 Volume Channel 2 +12 dB +11.875 dB +0.125 dB 0 dB -0.125 dB -114.125 dB -114 dB Mute Fast Mute 0000hex 11 MSBs (DPL 3519/20) 0006hex 11 MSBs (DPL 3519/20) 0111 1111 000x 0111 1110 111x 0111 0011 001x 0111 0011 000x 0111 0010 111x 7F0hex 7EEhex 732hex 730hex 72Ehex
0000 0001 001x 012hex 0000 0001 000x 010hex 0000 0000 xxxx 00xhex RESET 1111 1111 111x FFEhex
Example: Reduce Volume Reduce Tone Control
Vol.: +6 dB 3 6 4.5
Bass: +9 dB 9 6 7.5
Treble: +5 dB 5 5 5
The highest given positive 11-bit number (7F0hex) yields in a maximum possible gain of 12 dB. Decreasing the volume register by 1 LSB decreases the volume by 0.125 dB. Volume settings lower than the given minimum mute the output. With large scale input signals, positive volume settings may lead to signal clipping. With Fast Mute, volume is reduced to mute position by digital volume only. Analog volume is not changed. This reduces any audible DC plops. Going back from Fast Mute should be done to the volume step before Fast Mute was activated.
Compromise
9.1.2. Balance Channel 1 and Channel 2 Positive balance settings reduce the left channel without affecting the right channel; negative settings reduce the right channel leaving the left channel unaffected. In linear mode, a step by 1 LSB decreases or increases the balance by about 0.8% (exact figure: 100/127). In logarithmic mode, a step by 1 LSB decreases or increases the balance by 1 dB.
Clipping Mode Channel 1 Clipping Mode Channel 2 Reduce Volume Reduce Tone Control Compromise Mode
0000hex 3 LSBs (DPL 3519/20) 0006hex 3 LSBs (DPL 3519/20) x000 RESET x001 x010 0hex 1hex 2hex logarithmic Balance Mode Channel 1 Balance Mode Channel 2 linear 0001hex LSB (DPL 3519/20) 0030hex LSB (DPL 3519/20) xxx0 RESET xxx1 0hex 1hex
Micronas
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DPL 35xxA
PRELIMINARY DATA SHEET
Balance Channel 1 [L/R] Balance Channel 2 [L/R] Left muted, Right 100% Left 0.8%, Right 100% Left 99.2%, Right 100% Left 100%, Right 100% Left 100%, Right 99.2% Left 100%, Right 0.8% Left 100%, Right muted
0001hex H (DPL 3519/20) 0030hex H (DPL 3519/20) 0111 1111 0111 1110 0000 0001 0000 0000 RESET 1111 1111 1000 0010 1000 0001 7Fhex 7Ehex 01hex 00hex FFhex 82hex 81hex
9.1.3. Bass Channel 1 and Channel 2 Bass Channel 1 Bass Channel 2 +20 dB +18 dB +16 dB +14 dB +12 dB +11 dB +1 dB +1/8 dB 0002hex H (DPL 3519/20) 0031hex H (DPL 3519/20) 0111 1111 0111 1000 0111 0000 0110 1000 0110 0000 0101 1000 0000 1000 0000 0001 0000 0000 RESET 1111 1111 1111 1000 1010 1000 1010 0000 7Fhex 78hex 70hex 68hex 60hex 58hex 08hex 01hex 00hex FFhex F8hex A8hex A0hex
Balance Channel 1 [L/R] Balance Channel 2 [L/R] Left -127 dB, Right 0 dB Left -126 dB, Right 0 dB Left -1 dB, Right 0 dB Left 0 dB, Right 0 dB Left 0 dB, Right -1 dB Left 0 dB, Right -127 dB Left 0 dB, Right -128 dB
0001hex H (DPL 3519/20) 0030hex H (DPL 3519/20) 0111 1111 0111 1110 0000 0001 0000 0000 RESET 1111 1111 1000 0001 1000 0000 7Fhex 7Ehex 01hex 00hex FFhex 81hex 80hex
0 dB -1/8 dB -1 dB -11 dB -12 dB
With positive bass settings, internal overflow may occur even with overall volume less than 0 dB. This will lead to a clipped output signal. Therefore, it is not recommended to set bass to a value that, in conjunction with volume, would result in an overall positive gain. Loudspeaker channel: Bass and Equalizer cannot work simultaneously (see Table: Mode Tone Control). If Equalizer is used, Bass and Treble coefficients must be set to zero and vice versa.
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PRELIMINARY DATA SHEET
DPL 35xxA
9.1.5. Loudness Channel 1 and Channel 2 Loudness Channel 1 Loudness Channel 2 +17 dB +16 dB +1 dB 0 dB 0004hex H (DPL 3519/20) 0033hex H (DPL 3519/20) 0100 0100 0100 0000 0000 0100 0000 0000 RESET 44hex 40hex 04hex 00hex
9.1.4. Treble Channel 1 and Channel 2 Treble Channel 1 Treble Channel 2 +15 dB +14 dB +1 dB +1/8 dB 0 dB -1/8 dB -1 dB -11 dB -12 dB 0003hex H (DPL 3519/20) 0032hex H (DPL 3519/20) 0111 1000 0111 0000 0000 1000 0000 0001 0000 0000 RESET 1111 1111 1111 1000 1010 1000 1010 0000 78hex 70hex 08hex 01hex 00hex FFhex F8hex A8hex A0hex
Mode Loudness Channel 1 Mode Loudness Channel 2 Normal (constant volume at 1 kHz) Super Bass (constant volume at 2 kHz)
0004hex L (DPL 3519/20) 0033hex L (DPL 3519/20) 0000 0000 RESET 0000 0100 00hex 04hex
With positive treble settings, internal overflow may occur even with overall volume less than 0 dB. This will lead to a clipped output signal. Therefore, it is not recommended to set treble to a value that, in conjunction with volume, would result in an overall positive gain. Loudspeaker channel: Treble and Equalizer cannot work simultaneously (see Table: Mode Tone Control). If Equalizer is used, Bass and Treble coefficients must be set to zero and vice versa.
Loudness increases the volume of low and high frequency signals, while keeping the amplitude of the 1 kHz reference frequency constant. The intended loudness has to be set according to the actual volume setting. Because loudness introduces gain, it is not recommended to set loudness to a value that, in conjunction with volume, would result in an overall positive gain. By means of `Mode Loudness', the corner frequency for bass amplification can be set to two different values. In Super Bass mode, the corner frequency is shifted up. The point of constant volume is shifted from 1 kHz to 2 kHz.
Micronas
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DPL 35xxA
9.1.6. Spatial Effects Channel 1 Spatial Effect Strength Channel 1 Enlargement 100% Enlargement 50% Enlargement 1.5% Effect off Reduction 1.5% Reduction 50% Reduction 100% 0005hex H (DPL 3519/20) 0111 1111 0011 1111 0000 0001 0000 0000 RESET 1111 1111 1100 0000 1000 0000 7Fhex 3Fhex 01hex 00hex FFhex C0hex 80hex
PRELIMINARY DATA SHEET
There are several spatial effect modes available: Mode A (low byte = 00hex) is compatible to the formerly used spatial effect. Here, the kind of spatial effect depends on the source mode. If the incoming signal is in mono mode, Pseudo Stereo Effect is active; for stereo signals, Pseudo Stereo Effect and Stereo Basewidth Enlargement is effective. The strength of the effect is controllable by the upper byte. A negative value reduces the stereo image. A rather strong spatial effect is recommended for small TV sets where loudspeaker spacing is rather close. For large-screen TV sets, a more moderate spatial effect is recommended. In mode A, even in case of stereo input signals, Pseudo Stereo Effect is active, which reduces the center image. In Mode B, only Stereo Basewidth Enlargement is effective. For mono input signals, the Pseudo Stereo Effect has to be switched on. It is worth mentioning that all spatial effects affect amplitude and phase response. With the lower 4 bits, the frequency response can be customized. A value of 0000bin yields a flat response for center signals (L = R) but a high pass function of L or R only signals. A value of 0110bin has a flat response for L or R only signals but a lowpass function for center signals. By using 1000bin, the frequency response is automatically adapted to the sound material by choosing an optimal high pass gain.
Spatial Effect Mode Channel 1 Stereo Basewidth Enlargement (SBE) and Pseudo Stereo Effect (PSE). (Mode A) Stereo Basewidth Enlargement (SBE) only. (Mode B)
0005hex L (H nibble) (DPL 3519/20) 0000 RESET 0000 0010 0hex 0hex 2hex
Spatial Effect Customize Coefficient Channel 1 max high pass gain 2/3 high pass gain 1/3 high pass gain min. high pass gain automatic
0005hex L (L nibble) (DPL 3519/20) 0000 RESET 0010 0100 0110 1000 0hex 2hex 4hex 6hex 8hex
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PRELIMINARY DATA SHEET
DPL 35xxA
9.1.8. Channel Source Modes Channel 1 source 0007hex H (DPL 3519/20) 0000 0000 RESET 0100 0000 00hex 40hex Channel 2 source SCART source I2S1 source I2S2 source Quasi-peak detector source 0008hex H (DPL 3519/20) 0009hex H (DPL 3519/20) 000ahex H (DPL 3519/20) 000bhex H (DPL 3518/19/20) 0038hex H (DPL 3518/19/20) 000chex H (DPL 3518/19/20) 0000 0010 0000 0011 0000 0100 0000 0101 0000 0110 0000 0111 02hex 03hex 04hex 05hex 06hex 07hex
9.1.7. Volume SCART Channel Linear Mode Volume SCART OFF 0 dB gain (digital full scale (FS) to 2 VRMS output) +6 dB gain (-6 dBFS to 2 VRMS output)
0111 1111
7Fhex
Logarithmic Mode Volume SCART +12 dB +11.875 dB +0.125 dB 0 dB -0.125 dB -114.125 dB -114 dB Mute 0007hex 11 MSBs (DPL 3519/20) 0111 1111 000x 0111 1110 111x 0111 0011 001x 0111 0011 000x 0111 0010 111x 7F0hex 7EEhex 732hex 730hex 72Ehex
SCART DOLBYLR DOLBYCS I2S1 I2S2 DOLBYCSUB
(20) (18/19/20) (18/19/20) (18/19/20) (18/19/20) (18/19/20)
0000 0001 001x 012hex 0000 0001 000x 010hex 0000 0000 0000 000hex RESET
DOLBYLR denotes a signal pair consisting of surround decoder output for the left and right loudspeakers. The signal content depends on the used surround reproduction mode. DOLBYCS is the signal pair for the center and surround information (if there is any, depending on the surround reproduction mode). DOLBYCSUB is a signal pair consisting of the center information and a subwoofer channel. The subwoofer channel is the sum of all low frequency components (fg=100Hz) of the L, R and C channels. The I2S2 source must not be 00hex. It should be one of the mentioned values, otherwise the SCART source will not work properly. If the equalizer is switched on, SCART as source is no longer valid, i.e. AD input is no longer possible.
Volume Mode SCART linear logarithmic
0007hex LSB (DPL 3519/20) xxx0 RESET xxx1 0hex 1hex
Micronas
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DPL 35xxA
9.1.9. Channel Matrix Modes Channel 1 matrix Channel 2 matrix SCART matrix I2S1 matrix I2S2 matrix Quasi-peak detector matrix SOUNDA, LEFT or CENTER SOUNDB, RIGHT, SURROUND or SUBWOOFER STEREO MONO SUM/DIFF AB_XCHANGE PHASE_CHANGE_B PHASE_CHANGE_A A_ONLY B_ONLY INV_STEREO 0008hex L (DPL 3519/20) 0009hex L (DPL 3519/20) 000ahex L (DPL 3519/20) 000bhex L (DPL 3518/19/20) 0038hex L (DPL 3518/19/20) 000chex L (DPL 3518/19/20) 0000 0000 RESET 0001 0000 00hex 10hex
PRELIMINARY DATA SHEET
The sum/difference mode can be used together with the quasi-peak detector to determine the sound material mode. If the difference signal on channel B (right) is near to zero, and the sum signal on channel A (left) is high, the incoming audio signal is mono. If there is a significant level on the difference signal, the incoming audio is stereo. The inv_stereo mode can be used to phase invert outputs via the I2S interfaces. This gives the option to correct phase relations with outputs of attached processors.
9.1.10. SCART Prescale Volume Prescale SCART OFF 0 dB gain (2 VRMS input to digital full scale) 000dhex (DPL 3520) 0000 0000 RESET 0001 1001 0111 1111 H 00hex 19hex 7Fhex
0010 0000 0011 0000 0100 0000 0101 0000 0110 0000 0111 0000 1000 0000 1001 0000 1111 0000
20hex 30hex 40hex 50hex 60hex 70hex 80hex 90hex F0hex
+14 dB gain (400 mVRMS input to digital full scale)
9.1.11. I2S1 and I2S2 Prescale Volume Prescale I2S1 Volume Prescale I2S2 OFF 0 dB gain +18 dB gain 0016hex H (DPL 3518/19/20) 0012hex H (DPL 3518/19/20) 00hex 10hex RESET 7Fhex
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PRELIMINARY DATA SHEET
DPL 35xxA
9.1.13. Beeper Beeper Volume 0014hex H (DPL 3519/20) 0000 0000 RESET 0111 1111 00hex 7Fhex
9.1.12. ACB Register, Definition of the SCARTSwitches and DIG_CTR_OUT Pins ACB Register DFP In Selection SCART1_IN MONO_IN SCART2_IN SCART3_IN SCART1_OUT Selection SCART3_IN SCART2_IN MONO_IN DA_SCART SCART2_OUT Selection DA_SCART SCART1_IN MONO_IN DIG_CTR_OUT1 low high DIG_CTR_OUT2 low high 0013hex H (DPL 3519/20) xxxx xxxx xxxx xxxx xx00 xx01 xx10 xx11 RESET
OFF Maximum Volume (full digital scale FDS)
Beeper Frequency xxxx xxxx xxxx xxxx 00xx 01xx 10xx 11xx RESET 16 Hz (lowest) 1 kHz 4 kHz (highest) xx00 xxxx xx01 xxxx xx10 xxxx x0xx xxxx x1xx xxxx 0xxx xxxx 1xxx xxxx RESET
0014hex L (DPL 3519/20) 0000 0001 0100 0000 1111 1111 01hex 40hex FFhex
A squarewave beeper can be added to the loudspeaker channel and the headphone channel. The addition point is just before loudness and volume adjustment. 9.1.14. Mode Tone Control Mode Tone Control 00020hex H (DPL 3519/20) 0000 0000 RESET 1111 1111 00hex FFhex
RESET
RESET Bass and Treble
RESET: The RESET state is taken at the time of the first write transmission on the control bus to the audio processing part (DFP). By writing to the ACB register first, the RESET state can be redefined.
Equalizer
By means of `Mode Tone Control', Bass/Treble or Equalizer may be activated. The Equalizer must also not be used simultaneously with AD input (Source mode = SCART).
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DPL 35xxA
9.1.15. Equalizer Channel 1 Band 1 1 (below 120 Hz) Band 2 (center: 500 Hz) Band 3 (center: 1 500 Hz) Band 4 (center: 5 000 Hz) Band 5 (above 10 000 Hz) +12 dB +11 dB +1 dB +1/8 dB 0 dB -1/8 dB -1 dB -11dB -12 dB 00021hex (DPL 3519) 00022hex (DPL 3519) 00023hex (DPL 3519) 00024hex (DPL 3519) 00025hex (DPL 3519) 0110 0000 0101 1000 0000 1000 0000 0001 0000 0000 RESET 1111 1111 1111 1000 1010 1000 1010 0000 H H H H H 60hex 58hex 08hex 01hex 00hex FFhex F8hex A8hex A0hex
PRELIMINARY DATA SHEET
9.1.16. Surround Decoder Modes Surround Decoder Modes ADAPTIVE (Dolby Pro Logic) PASSIVE EFFECT 0040hex H (DPL 3518/19/20) 0000 0000 RESET 0001 0000 0010 0000 00hex 10hex 20hex
The surround decoder mode specifies which method is being used to create four output channels out of two input channels. For Dolby Pro Logic operation the matrix must be switched to ADAPTIVE. Even sound material not encoded in Dolby Surround will produce good surround effects in this mode. All surround reproduction modes can be used together with the ADAPTIVE mode. The PASSIVE mode should only be used together with WIDE mode. The EFFECT mode is intended to get surround effects even in case of mono transmissions (Note: For mono signals, Dolby Pro Logic will only reproduce signals via the center channel. All other channels will be muted). For a more detailed description see section 10.2. "Useful combinations of the surround decoder and reproduction modes".
With positive equalizer settings, internal overflow may occur even with overall volume less than 0 dB. This will lead to a clipped output signal. Therefore, it is not recommended to set Equalizer bands to a value that, in conjunction with volume, would result in an overall positive gain. The Equalizer must not be used simultaneously with Bass and Treble (Mode Tone Control must be set to FF to use the Equalizer). If Bass and Treble are used, Equalizer coefficients must be set to zero. The Equalizer must also not be used simultaneously with AD input (Source mode = SCART).
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PRELIMINARY DATA SHEET
DPL 35xxA
9.1.18. Surround Source Modes Surround Source Modes NOISE SCART
(18/19/20) (20) (18/19/20) (18/19/20)
9.1.17. Surround Reproduction Modes Surround Reproduction Modes NORMAL PHANTOM WIDE THREE_CHANNEL CENTER_OFF PANORAMA 0040hex L (DPL 3518/19/20) 0000 0000 RESET 0001 0000 0010 0000 0011 0000 0100 0000 0101 0000 00hex 10hex 20hex 30hex 40hex 50hex
0041hex H (DPL 3518/19/20) 0000 0001 0000 0010 0000 0101 0000 0110 01hex 02hex 05hex 06hex
I2S1 I2S2
Select the source to be fed to the surround decoder block. The NOISE mode selects a built-in noise generator. If the equalizer is switched on, SCART as source is no longer valid, i.e. AD input is no longer possible. 9.1.19. Surround Source Matrix Modes Surround Source Matrix (Sound Source) SOUNDA SOUNDB STEREO MONO Surround Source Matrix (Noise Source) NOISE_L NOISE_C 0041hex L (DPL 3518/19/20) 0000 0000 RESET 0001 0000 0010 0000 0011 0000 00hex 10hex 20hex 30hex
The standard mode to reproduce Dolby Pro Logic Surround is NORMAL. All four channels L, C, R, S are in operation. Low Frequency signals of the C channel are distributed to the L and R loudspeakers. This enables the center speaker to be a smaller model than the L and R speaker. If all three front speakers are identical and capable of reproducing low bass information, and if equal power is available in the L, C and R amplifiers, then it may be beneficial to use the WIDE mode. The center channel will then contain the full frequency range signal. The NORMAL and WIDE modes using 4 or 5 loudspeakers give the optimum solution for surround reproduction. Other modes using less loudspeakers create inferior surround effects. If no center speaker is available, the PHANTOM mode prevents loss of the center information by splitting it up equally to the L and R speakers. If no surround speaker is available the THREE_CHANNEL mode can be used. This mode will confine the sound to the front speakers. The CENTER_OFF mode provides a simple way to optimize the manual input balance. While switched off, the balance control can be adjusted for minimum dialogue level. Surround sound can be reproduced to a certain extent even with two loudspeakers. The PANORAMA mode mixes all four surround decoder outputs to the L and R output channel without any loss of information.
0041hex L (DPL 3518/19/20) 1010 0000 1011 0000 1100 0000 1101 0000 a0hex b0hex c0hex d0hex
NOISE_R NOISE_S
Select the mode of the sound source. Real Dolby Pro Logic Surround sound can only be displayed in the STEREO mode. Mono modes such as SOUNDA, SOUNDB and MONO will not produce a surround effect unless the surround decoder mode is switched to EFFECT. If the equalizer is switched on, the SCART source mode is no longer valid. The modes NOISE_L, NOISE_C, NOISE_R and NOISE_S create an input signal to the decoder that will result in a noise signal on the L, C, R and S outputs.
Micronas
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DPL 35xxA
9.1.20. Surround Delay Surround Delay 5 ms (lowest) 6 ms 31 ms (highest) 0042hex H (DPL 3518/19/20) 0000 0101 0000 0110 0001 1111 05hex 06hex
PRELIMINARY DATA SHEET
Increases the perceived basewidth of the reproduced left and right front channels. Recommended value: 50% = 40hex. In contrast to the spatial effect for channel 1, the surround spatial effect is optimized for Dolby Pro Logic. The difference is most obvious for the Phantom and Panorama reproduction modes.
9.1.24. Panorama Sound Effect 1Fhex Panorama Sound Effect OFF 9.1.21. Surround Manual Input Balance 0.8% Surround Manual Input Balance Left muted, Right 100% Left 0.8%, Right 100% Left 99.2%, Right 100% Left 100%, Right 100% Left 100%, Right 99.2% Left 100%, Right 0.8% Left 100%, Right muted 0043hex H (DPL 3518/19/20) 0111 1111 0111 1110 0000 0001 0000 0000 RESET 1111 1111 1000 0010 1000 0001 7Fhex 7Ehex 01hex 00hex FFhex 82hex 81hex 9.1.25. Surround Reverberation Surround Reverberation OFF 0.8% 99.2% 100% 0046hex H (DPL 3518/19/20) 0000 0000 RESET 0000 0001 0111 1110 0111 1111 00hex 01hex 7Ehex 7Fhex Strength of the surround effect in PANORAMA mode. Recommended value: 66% = 54hex. Delay should be set to the max. value: 31 ms and reverberation should be off. This register only has the correct effect in PANORAMA mode (Surround Reproduction Mode is set to PANORAMA). It must be zero (OFF) in non PANORAMA modes) 99.2% 100% 0045hex H (DPL 3518/19/20) 0000 0000 RESET 0000 0001 0111 1110 0111 1111 00hex 01hex 7Ehex 7Fhex
For Dolby Pro Logic designs, only 20 ms fixed or 15-30 ms variable delay must be used.
In automatic balance mode this register has no effect. 9.1.22. Surround Input Balance Mode Surround Input Balance Mode Automatic balance Manual balance 0043hex L (DPL 3518/19/20) 0000 0000 0100 0000 00hex 40hex
Automatic balance mode is recommended. 9.1.23. Surround Spatial Effect Surround Spatial Effect OFF 0.8% 99.2% 100% 0044hex H (DPL 3518/19/20) 0000 0000 RESET 0000 0001 0111 1110 1111 1111 00hex 01hex 7Ehex 7Fhex
Reverberation will be added to the surround channel. Due to the maximally implemented 31 ms only dry sounds will be affected. The effect will be rather weak for source material which already contains a certain amount of reverberation. It can be used to create a more reverberant sound when using the EFFECT decoder mode for mono signals. Recommended value: not more than 66% = 54hex. Delay should be set to the maximum value: 31 ms.
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PRELIMINARY DATA SHEET
DPL 35xxA
9.2. Summary of Readable Registers All readable registers are 16-bit wide. Transmissions via I2C-bus have to take place in 16-bit words. These registers are not writable. Name Digital input level register Quasi peak readout left Quasi peak readout right Address 0018hex 0019hex 001ahex High/Low H H&L H&L [00hex ... 7FFFhex] [00hex ... 7FFFhex] Output Range single bits 16-bit two's complement 16-bit two's complement
9.2.1. Quasi Peak Detector Quasi peak readout left Quasi peak readout right Quasi peak readout 0019hex H+L (DPL 3518/19/20) 001ahex H+L (DPL 3518/19/20) [0hex ... 7FFFhex] values are 16-bit two's complement
9.2.2. Digital Input Level Register Used to read back the input level of certain digital input pins: Pin D_CTR_IN D_CTR_IO1 D_CTR_IO0 Bit X--- -X-- --X- ---- ---- ----
The quasi peak readout register can be used to read out the quasi peak level of any input source, in order to adjust all inputs to the same normal listening level. The refresh rate is 32 kHz. The feature is based on a filter time constant: attack-time: 1.3 ms decay-time: 37 ms
A high level on the input pins gives a "1", a low level gives "0".
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10. Further Explanations and Application Hints 10.1. Overview of the Surround Decoder and Reproductions Modes The register 0040hex H "surround decoder modes" define which method should be used to create a multichannel signal out of an stereo input. The register 0040hex L "sound reproduction modes" define which method should be used to mix the multichannel output to the actually used loudspeakers (or final output channels).
PRELIMINARY DATA SHEET
L Lt Surround Decoder Mode Rt L R C S S
All outputs used No center speaker used No surround speaker used Only Left/Right speaker used
L R
L R C
L R
Surround Reproduction Mode
R C
S
Fig. 10-1: Surround Decoder and Reproduction Mode Principle
The PANORAMA sound reproduction mode mixes all 4 channels into 2 output channels. Fig 10-2 gives the internal processing of this mode. All other reproduction modes are according to the Dolby specification. L R C
2 -3dB 2
L' R'
L'' R''
S
SL
PANORAMA Sound Algorithm
SR
Panorama Sound Effect (Register 45hex)
Fig. 10-2: Surround Spatial Effect and PANORAMA Sound Processing
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PRELIMINARY DATA SHEET
DPL 35xxA
10.2.2. Useful Combinations with the PASSIVE Surround Decoder Mode The passive surround decoder (which is defined by Dolby) uses no center speaker! In no cases, a center speaker should be connected to the output (or if, the center speaker should be muted). Only two modes are useful (all other modes give inferior results!): WIDE L, R and S speakers used. Do not connect speakers to the center channel only L and R speaker used (creates a surround like effect with only 2 speakers, result is inferior to the combination with the ADAPTIVE mode)
10.2. Useful Combinations of the Surround Decoder and Reproduction Modes In principle, the "surround decoder modes" and the "sound reproduction modes" modes could be orthogonal (all "surround decoder modes" can be used with all "sound reproduction modes") but there are some combinations that do not create "good" sound. 10.2.1. Useful Combinations with the ADAPTIVE Surround Decoder Mode NORMAL all output channels used, L and R speakers have better bass capability
PANORAMA
WIDE
all output channels used, L,R and C speakers all have good bass capability no center speaker used (note: the center output channel C is muted automatically)
10.2.3. Useful Combinations with the EFFECT Surround Decoder Mode The EFFECT surround decoder mode is intended for MONO sources. MONO sources give no surround effect in the ADAPTIVE and PASSIVE modes. In order to give the customer means to create surround sound even in presence of mono signals, the EFFECT mode can be used. NORMAL all output channels used, L and R speakers have better bass capability. The center channel may need a lower volume to compensate for the dominant center. all output channels used, L,R and C speakers all have better bass capability. The center channel may need a lower volume to compensate for the dominant center. or: no center speaker used (no center speaker connected) PANORAMA only L and R speaker used (creates a surround like effect with only 2 speakers, result is inferior to the combination with the ADAPTIVE mode)
PHANTOM
THREE_CHANNEL no surround speaker used (creates a STEREO like effect, but with better center stage reproduction) (Note: the surround output channel is not automatically muted) CENTER_OFF systems with center speaker, only for adjustment of manual input balance. (Note: Dolby suggests to use the adaptive input balance always) only L and R speaker used (creates a surround like effect with only 2 speakers) (Note: the left and right output channels L&R are not muted automatically)
WIDE
PANORAMA
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10.3. Further Notes 1. The ADAPTIVE mode seems to get better results compared to the PASSIVE in all cases, even for source signals that are not encoded in Dolby Surround. 2. Using the EFFECT mode for mono signals creates a very dry surround signal. This can be somewhat compensated with the Surround Reverberation Register (0046hex H). 3. For small speaker spacing the perceived basewidth can be increased by using Surround Spatial Effect (Register 0044hex H). This also works best for the ADAPTIVE mode. 4. Surround Spatial Effect can be used in combination with PANORAMA. This also works best for the ADAPTIVE mode. 5. The adaptive input balance is recommended for the ADAPTIVE mode. In PASSIVE or EFFECT mode, the input balance can be switched to manual in middle position. 6. In PANORAMA mode, the strength of the surround signal can be controlled by the Panorama Sound Effect Register (0045hex H). In other modes, this register has no effect and should be set to 0. 10.4. Input and Output Levels for Dolby Pro Logic Operation The analog inputs are able to accept 2 Vrms input level without overloading any stage before the volume control. The nominal input level (input sensitivity) is 350 mV. This gives 15 dB headroom. The scart prescale value should be set to 0 dB (25dec). I2S-inputs should have the same headroom when entering the DPL. The nominal input level is -15 dBFS. The highest possible input level of 0 dBFS is accepted without internal overflow. The I2S-prescale value should be set to 0 dB (25dec).
PRELIMINARY DATA SHEET
With higher prescale values lower input sensitivities can be accommodated. A higher input sensitivity is not possible, because at least 15 dB headroom is required for every input according to the Dolby specifications. A full-scale left only input (2 Vrms) will produce a fullscale left only output with 0 dB volume. The typical output levels are 1.37 Vrms for channel 1 and 2 and 1.9 Vrms for SCART outputs. The I2S-channels yield 0 dBFS. The same holds true for right only signals. A fullscale input level on both inputs (Lin=Rin=2 Vrms) will give a center only output with maximum level. The typical output levels are 1.37 Vrms for channel 1 and 2 outputs and 1.9 Vrms for SCART outputs. The I2S-channels yield 0 dBFS. A full-scale input level on both inputs (but Lin and Rin with inverted phases) will give a surroundonly signal with maximum level. For reproducing Dolby Pro Logic according to its specifications, the center and surround outputs must be amplified by 3 dB with respect to the L and R output signals. This can be done in two ways: 1. By implementing 3 dB more amplification for center and surround loudspeaker outputs. 2. By always selecting volume for L and R 3 dB lower than center and surround. Method 1 is preferable, as method 2 lowers the achievable SNR for left and right signals by 3 dB. 10.5. Dolby Qualification Qualification testing for Dolby approval requires the device to be switched to plain Dolby Pro Logic without any sound effects. Effects, such as PANORAMA, Surround Spatial Effect or Surround Reverberations must be switched off. The surround decoder must be switched to ADAPTIVE. For Dolby Pro Logic designs only 20 ms fixed or 15-30 ms variable delay must be used.
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PRELIMINARY DATA SHEET
DPL 35xxA
10.6. Phase Relationship of Outputs The analog output signals channel 1, channel 2 and SCART2 of the DPL all have the same phases. The user does not need to correct output phases when using these analog outputs directly. The SCART1 output has opposite phase. Using the I2S-outputs for other DSPs or D/A converters, care has to be taken to adjust for the correct phase. If the attached coprocessor is one of the MSP family, the following schematics help to determine the phase relationship:
I2Sin
I2Sout
DFP - MONO SCART1 & 2 & 3 -
Channel1 & 2, Main, Aux SCART2 SCART1 SCART1 & 2
Fig. 10-3: Phase Diagram of DPL, MSPB, MSPC (>c6) and MSPD
I2Sin
I2Sout
- - DFP - Channel1 & 2, Main, Aux SCART2 SCART1 MONO SCART1 & 2 & 3 - SCART1 & 2
Fig. 10-4: Phase Diagram of MSPC (xc6)
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10.7. Minimum Control Transmissions for the DPL 3520A The following listing contains the minimum data transfer for setting up the DPL in stand alone mode. The file resets registers even though these registers are already reset by the hardware reset. This is to ensure, that even without external reset, the original state is restored. Note: the trap is the transmission to register 56dez=38hex. This register must not be 0 (which it is after reset). This is mentioned in the data sheet on page 39 (9.1.8. channel source modes). The format of the listing is the same as the log format of our demo software (without the comments). You can create a file with these transmission codes and execute it via our demo software. Use the I2C -> Init from File - menu. 16, 131, 0, 38
PRELIMINARY DATA SHEET
18, 0, 103, 0 18, 1, 0, 0 18, 2, 0, 0 18, 3, 0, 0 18, 4, 0, 0 18, 5, 0, 0 18, 6, 103, 0 18, 7, 103, 1 18, 8, 3, 32 18, 9, 4, 32 18, 10, 7, 16 18, 13, 29, 0 18, 19, 12, 0
18, 32, 0, 0 18, 48, 0, 0 18, 49, 0, 0 18, 50, 0, 0 18, 51, 0, 0 18, 56, 2, 0
18, 64, 0, 0
18, 65, 2, 32 18, 66, 18, 0 18, 67, 0, 0 18, 68, 0, 0 18, 69, 0, 0 18, 70, 0, 0
! 131=83hex = MODE_REG: ! dig_out, i2s and audioclock out set ! to tristate, i2s master, i2s sony ! mode ! volume channel1 = -12dB ! balance channel1 = 0dB/0dB ! bass channel1 = 0dB ! treble channel1 = 0dB ! loudness channel1 = 0dB ! spat effect channel1 off ! volume channel2 = -12dB ! volume SCART = -12dB ! channel1 source = DOLBYLR, ! matrix = STEREO ! channel2 source = DOLBYCS, ! matrix = STEREO ! SCART source = DOLBYCSUB, ! matrix = SOUNDB (=subwoofer) ! prescale SCART = 29dez ! ACB: SCART2_OUT, ! SCART1_OUT=DA_SCART ! (=subwoofer), DFPin=SCART1_IN ! (=Lt, Rt input to SCART1) ! Tone control = bass/treble ! balance channel2 = 0dB/0dB ! bass channel2 = 0dB ! treble channel2 = 0dB ! loudness channel2 = 0dB ! I2S2 source = SCART ! ! although this is not used it must be ! set ! ! surround decoder mode = ! ADAPTIVE, Surround ! reproduction mode = NORMAL ! Surround Source = SCART, ! surround source mode = STEREO ! surround delay = 24ms ! surround input balance mode = ! AUTOMATIC ! surround spatial effect = off ! panorama sound effect = off ! surround reverberation = off
format: <16|18>, , , 16 means: write transmission to MODEREG 18 means: write transmission to DFP all values in decimal
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PRELIMINARY DATA SHEET
DPL 35xxA
11. Application Principle of the DPL 3520A L or L+C or PSL
SCART1 2 2 2
R or R+C or PSR DPL 3520A Dolby Pro Logic
2
Line Inputs
SCART2 SCART3
C S
SCART
Line Outputs
Fig. 11-1: Standard configuration
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12. Application Circuit Diagram of the DPL 3520A
PRELIMINARY DATA SHEET
18.432 MHz Clock
0:10 pF >1nF 10 F + 3.3 100 F nF + 18.432 MHz + + 10 F 10 F
+8.0 V
XTAL_IN (62) 21 Alternative circuit for external clock input AGNDC (42) 42 XTAL_IN (62) 21 CAPL_C1 (40) 44 XTAL_OUT (63) 20 VREFTOP (54) 29 CAPL_C2 (38) 46
28 (55) MONO_IN 330 nF AHVSS 330 nF 31 (52) SC1_IN_L 330 nF AHVSS 330 nF 34 (49) SC2_IN_L 330 nF AHVSS 330 nF 37 (46) SC3_IN_L 330 nF 35 (48) ASG2 DACC2_R (25) 60 36 (47) SC3_IN_R 1 nF 1 nF 32 (51) ASG1 33 (50) SC2_IN_R DACC2_L (26) 59 1 nF DACC1_R (28) 57 52 (30) ASG3 30 (53) SC1_IN_R 1 nF DACC1_L (29) 56
1F 1F
1F 1F
DPL 3520A
5V
11 (7) STANDBY Q SC1_OUT_L (37) 47 SC1_OUT_R (36) 48
100 22 F 100 22 F
+ +
5V
DVSS DVSS 12 (6) ADR_SEL
SC2_OUT_L (34) 50 9 (9) I2C-CL 8 (10) I2C-DA SC2_OUT_R (33) 51 D_CTR_IN (64) 19 6 (12) I2S_WS 7 (11) I2S_CL 4 (14) I2S_DA_IN1 65 (20) I2S_DA_IN2 5 (13) I2S_DA_OUT 64 (21) I2S_DA_OUT2 61 (24) RESETQ 45 (39) AHVSUP 67 (18) DVSUP 26 (57) AVSUP D_CTR_IO0 (5) 13 D_CTR_IO1 (4) 14 AUD_CL_OUT (1) 18
100 22 F
+
100 22 F
+
TESTEN (61) 22 43 (41) AHVSS 49 (35) VREF1 58 (27) VREF2 DVSS
66 (19) DVSS
100 nF + 10 F 100 nF AVSS 100 nF
5V
5V
27 (56) AVSS
8.0 V
Note: Pin numbers refer to the PLCC68 package, numbers in brackets refer to the PSDIP64 package.
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PRELIMINARY DATA SHEET
DPL 35xxA
13. Dolby Pro Logic Processor Family 13.1. DPL 3518A: Basic Dolby Pro Logic Coprocessor for the MSP Family
DPL 3518A Dolby Pro Logic I2S Tuner L or L+C or PSL R or R+C or PSR Tuner MSP 3400 C or MSP 3410 D
SCART1 2 2 2 2 2 SCART1 SCART2
I2S
C S
Line Inputs
SCART2 SCART3
Line Outputs
Fig. 13-1: Standard configuration
I2S_DA_OUT1 I2S_DA_OUT2 2S_DA_IN2 I I2S_CL I2S_WS
I2S_DA_IN1
I2S-Interface
I2S1/2L/R I2S1/2L/R
DSP
Fig. 13-2: Architecture of the DPL 3518A
I2S1L I2S1R I2S2L I2S2R Prescale I2S2 Channel Matrix Channel Select I2S2L I2S2R Prescale I2S1 Channel Matrix I2S1L I2S1R
I2S1 Output
I2S-Bus Inputs
I2S2 Output
L/L + C/PSL Surround Source Select Dolby Pro Logic Surround Source Matrix Passive Effect C SUB R/R + C/PSR C SR
Quasi-Peak Channel Matrix
Quasi peak readout L Quasi-Peak Detector Quasi peak readout R
I2S1L
Internal signal lines
Noise Generator
Fig. 13-3: Baseband processing of the DPL 3518A
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13.2. DPL 3519A: Advanced Dolby Pro Logic Coprocessor for the MSP Family
PRELIMINARY DATA SHEET
C DPL 3519A Dolby Pro Logic SUB SL SR I2S Tuner L or L+C or PSL MSP 3410 B or MSP 3400 B or MSP 3400 C or MSP 3410 D
2 2 SCART1 SCART2
I2S
R or R+C or PSR
Tuner
Headphone
SCART1
2 2 2
Line Inputs
SCART2 SCART3
Line Outputs
Fig. 13-4: Standard configuration
I2S_DA_OUT1 I2S_DA_IN1
I2S_DA_OUT2
I2S_CL I2S_WS
I2S_DA_IN2
I2S-Interface
I2S1/2L/R I2S1/2L/R FM1 OUT1_L OUT1_R
D/A D/A D/A D/A
OUT1_L OUT1_R
Channel 1 Output
Mono
MONO_IN
OUT2_L OUT2_R
OUT2_L OUT2_R
Channel 2 Output
SC1_IN_L SCART1 SC1_IN_R
DSP
SCART_L SCART_R
D/A D/A
SC2_IN_L SCART2 SC2_IN_R SC3_IN_L SCART3 SC3_IN_R
SC1_OUT_L SCART 1 SC1_OUT_R
SC2_OUT_L SCART 2 SC2_OUT_R
SCART Switching Facilities
Fig. 13-5: Architecture of the DPL 3519A
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PRELIMINARY DATA SHEET
DPL 35xxA
Channel1 Matrix
Equalizer or Bass/Treble Loudness Spatial Effects
Volume
OUT1L
Channel 1 Output
Bass,Treble Loudness Spatial Effects I2S1L I2S1R I2S2L I2S2R Channel Select SCART Channel Matrix Channel2 Matrix Prescale Bass,Treble Loudness Prescale
Balance
OUT1R
I2S-Bus Inputs
Volume Balance
OUT2L OUT2R
Channel 2 Output
Volume
SCARTL SCARTR
SCART Output
L/L + C/PSL Surround Source Select R/R + C/PSR Dolby Pro Logic or Passive or Effect
I2S1 Channel Matrix
I2S1L I2S1R
I2S1 Output
Surround Source Matrix
C SR C SUB I2S2 Channel Matrix I2S2L I2S2R I2S2 Output
Noise Generator
QuasiPeak Channel Matrix
Quasi peak readout L Quasi-Peak Detector Quasi peak readout R
I2S1L
Internal signal lines
Fig. 13-6: Baseband processing of the DPL 3519A
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14. IC Failure Report Three errors have been detected on the A1 versions of following ICs: DPL 3518A, DPL 3519A, and DPL 3520A. 1. The register for the I2S2 channel source does not work. Instead of using register 38hex, register 0chex (Quasi peak detector source) is used. So, the I2S2 source is always the same as the source for the Quasi peak detector. Nevertheless 38hex must be programmed to a value other than the reset state of 00hex (See note in chapter 9.1.8.). 2. If the DPL is used with manual input balance, the lower 4 bits in register 43 must be zero. Only the upper 4 bits can be programmed. 3. The fast mute feature (registers 00hex and 06hex) does not work. Use normal mute instead. These errors will be corrected with version A2. 15. Data Sheet History
PRELIMINARY DATA SHEET
1. Preliminary Data Sheet: "DPL 3520A, DPL 3519A, DPL 3518A Dolby Pro Logic Processor Family", July 31, 1997, 6251-423-1PD. First release of the preliminary data sheet.
Micronas GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@micronas.com Internet: www.micronas.com Printed in Germany Order No. 6251-423-1PD
All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. No part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of Micronas GmbH.
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